Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 524 of 1004
REJ09B0301-0400
17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the host interface.
(Internal interrupt signals)
IBF2 IBF1
Control
logic
HDB7 to HDB0
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
Module data bus
Host data bus
Host
interrupt
request
Fast
A20
gate
control
Port 4, Port 8
Internal data bus
Bus
interface
CS1
C
S2/ECS2
IOR
IOW
HA0
HIRQ1
HIRQ11
HIRQ12
GA20
HIFSD
Legend:
IDR1:
IDR2:
ODR1:
ODR2:
STR1:
STR2:
HICR:
Input data register 1
Input data register 2
Output data register 1
Output data register 2
Status register 1
Status register 2
Host interface control register
Figure 17.1 Block Diagram of Host Interface