To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2140B Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2161B H8S/2160B H8S/2141B H8S/2140B H8S/2145B HD64F2161BV HD64F2160BV HD64F2141BV HD64F2140BV HD64F2145BV HD64F2145B H8S/2148B HD64F2148BV HD64F2148B Rev.3.00 2006.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7.
Preface The H8S/2140B Group are microcomputers (MCUs) made up of the H8S/2000 CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. • In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 27, List of Registers.
Main Revisions for This Edition Item Page Revision (See Manual for Details) All — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8S/2140B Series → (After) H8S/2140B Group 1.1 Features 1 • Various peripheral functions Note * added Host Interface LPC interface* Note: * The LPC function is not supported by H8S/2148B and H8S/2145B (5-V version).
Item Page Revision (See Manual for Details) 1.3.1 Pin Arrangement 5 Note amended Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-V version). Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B 1.3.2 Pin Functions in 11 Each Operating Mode Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode 2.4.
Item Page Revision (See Manual for Details) 2.7.9 Effective Address Calculation 56 Table amended 8 Table 2.13 Effective Address Calculation (2) Memory indirect @@aa:8 • Normal mode op abs • Advanced mode op 3.4 Address Map in Each Operating Mode abs 77, 78 Figure 3.7 and Figure 3.8 added 79 Figure 3.9 amended Figure 3.7 Address Map for H8S/2145B (1) Figure 3.8 Address Map for H8S/2145B (2) Figure 3.9 Address Map for H8S/2148B(1) H'01FFFF H'020000 H'FFE080 4.7 Usage Note 87 Figure 4.
Item Page Revision (See Manual for Details) 5.6 Interrupt Control Modes and Interrupt Operation 105 Table amended Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. Table 5.4 Interrupt Control Modes 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR. 5.6.5 DTC Activation by Interrupt 114 7.2.
Item Page Revision (See Manual for Details) 8.9.3 Pin Functions 197 2 • P83/LPCPD* Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 198 2 • P82/HIFSD/CLKRUN* Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). 199 3 • P80/HA0/PME* Note 3 amended Note: 3. Not supported by the H8S/2148B and H8S/2145B (5-V version). 8.12.
Item Page Revision (See Manual for Details) 14.4.2 Interval Timer Mode 354 Figure 14.4 amended φ Figure 14.4 OVF Flag Set Timing TCNT H'FF H'00 Overflow signal (internal signal) OVF 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment 357 Figure 14.7 amended TCNT write cycle T1 T2 φ Figure 14.7 Conflict between TCNT Write and Increment Address Internal write signal 15.1 Features 360 2 16.3.
Item Page 2 16.3.5 I C Bus Register (ICCR) Revision (See Manual for Details) 427, 428 Table amended 2 Bit 1 R/W of I C Bus Interface Interrupt Request Flag (Before) R/W → (After) R/(W)* Table 16.5 Flash and Transfer States (Slave Mode) 16.4.4 Master Receive Operation 430 451 Figure 16.12 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) Table 16.
Item Page Revision (See Manual for Details) 16.4.4 Master Receive Operation 453 Figure 16.15 amended Read ICDR Figure 16.15 Sample Flowchart for Operations in Master Receive (Receiving a Single Byte) (WAIT = 1) [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) IRIC = 1? Yes Set ACKB = 1 in ICSR Figure 16.
Item Page Revision (See Manual for Details) 17.3.1 Keyboard Control Register H (KBCRH) 492 Table amended Bit Bit Name Initial Value R/W Description 6 KCLKI 1 R Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 19.4.4 Host Interface Shutdown Function (LPCPD) 569 Table 19.
Item Page Revision (See Manual for Details) 23.8.1 Program/ Program-Verify 625 Figure 23.11 amended Start of programming Write pulse application subroutine Figure 23.11 Program/ProgramVerify Flowchart Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Item Page Revision (See Manual for Details) 25.1.1 Standby Control Register (SBYCR) 643 Table amended STS2 STS1 STS0 Wait Time 20 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit 0 0.4 1.3 2.0 4.1 ms 0 0 8192 states 0.8 1.0 Table 25.1 Operating Frequency and Wait Time 26.1 Register Addresses (Address Order) 670 26.2 Register Bits 679 Note 2 amended Note: 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Note 5 amended Note: 5.
Item Page Revision (See Manual for Details) 27.1.6 Flash Memory Characteristics 722 Table 28.15 amended Table 27.15 Flash Memory Characteristics 723 Item Symbol Min Typ Programming time*1 *2 *4 Max Unit tP — Erase time*1 *3 *6 tE — 10 200 ms/ 128 bytes 100 1200 ms/block Reprogramming count NWEC 100*8 10,000*9 — times Data retention time*10 tDRP 10 Years — — Test Condition Notes 8 to 10 added Notes: 8.
Item Page Revision (See Manual for Details) 27.3.1 Clock Timing 762 Figure 27.7 amended Figure 27.
Rev. 3.
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Features ............................................................................................................................. 1 Block Diagram .................................................................................................................. 3 Pin Arrangement and Functions..............................................................
2.8 2.9 2.7.8 Memory Indirect—@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Notes ...................................................................................................................... 2.9.
5.3.4 5.3.5 5.3.6 5.3.7 5.4 5.5 5.6 5.7 5.8 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... IRQ Enable Register (IER) .................................................................................. IRQ Status Register (ISR).................................................................................... Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) .......................................
6.6 6.7 6.8 6.5.3 Basic Operation Timing ....................................................................................... 6.5.4 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 6.6.1 Basic Operation Timing ....................................................................................... 6.6.
7.8.4 7.8.5 Setting Required on Entering Subactive Mode or Watch Mode .......................... 166 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ........ 166 Section 8 I/O Ports .............................................................................................................. 167 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Overview........................................................................................................................... Port 1.............
8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 Port 8................................................................................................................................. 8.9.1 Port 8 Data Direction Register (P8DDR)............................................................. 8.9.2 Port 8 Data Register (P8DR)................................................................................ 8.9.3 Pin Functions ..........................................................................................
Section 9 8-Bit PWM Timer (PWM) ............................................................................. 231 9.1 9.2 9.3 9.4 9.5 Features ............................................................................................................................. Input/Output Pin................................................................................................................ Register Descriptions ..........................................................................................
11.5.1 FRC Increment Timing ........................................................................................ 11.5.2 Output Compare Output Timing .......................................................................... 11.5.3 FRC Clear Timing................................................................................................ 11.5.4 Input Capture Input Timing ................................................................................. 11.5.5 Buffered Input Capture Input Timing .....
12.6.1 16-Bit Count Mode .............................................................................................. 12.6.2 Compare-Match Count Mode .............................................................................. 12.7 Input Capture Operation.................................................................................................... 12.8 Interrupt Sources............................................................................................................... 12.9 Usage Notes .
14.4 Operation .......................................................................................................................... 14.4.1 Watchdog Timer Mode ........................................................................................ 14.4.2 Interval Timer Mode ............................................................................................ 14.4.3 RESO Signal Output Timing ............................................................................... 14.5 Interrupt Sources...
15.6.2 15.6.3 15.6.4 15.6.5 SCI Initialization (Clocked Synchronous Mode) ................................................. Serial Data Transmission (Clocked Synchronous Mode) .................................... Serial Data Reception (Clocked Synchronous Mode).......................................... Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 15.7 IrDA Operation ..............................
16.4.11 Initialization of Internal State .............................................................................. 16.5 Interrupt Sources............................................................................................................... 16.6 Usage Notes ...................................................................................................................... 16.6.1 Module Stop Mode Setting ..................................................................................
18.5.1 IBF1, IBF2, IBF3, and IBF4 ................................................................................ 18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 18.6 Usage Notes ...................................................................................................................... 18.6.1 Note on Host Interface ......................................................................................... 18.6.2 Module Stop Mode Setting .............
20.5.1 Module Stop Mode Setting .................................................................................. 583 Section 21 A/D Converter ................................................................................................. 585 21.1 Features ............................................................................................................................. 21.2 Input/Output Pins ......................................................................................................
23.8 23.9 23.10 23.11 23.12 23.7.1 Boot Mode ........................................................................................................... 23.7.2 User Program Mode............................................................................................. Flash Memory Programming/Erasing ............................................................................... 23.8.1 Program/Program-Verify ..................................................................................... 23.8.
25.10 Module Stop Mode ........................................................................................................... 25.11 Direct Transitions.............................................................................................................. 25.12 Usage Notes ...................................................................................................................... 25.12.1 I/O Port Status......................................................................................
Index .......................................................................................................................................... 783 Rev. 3.
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B.................................................................................................... Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B ..................................... Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ..... Figure 1.4 Pin Arrangement of H8S/2160B and H8S/2161B................................................
Figure 4.3 Operation when SP Value Is Odd ........................................................................ 87 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB...................................................................................................
Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 DTC Operation Flowchart ................................................................................... Memory Mapping in Normal Mode..................................................................... Memory Mapping in Repeat Mode...................................................................... Memory Mapping in Block Transfer Mode .........................................................
Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) ............................................. 282 Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) .................................................... 283 Section 12 8-Bit Timer (TMR) Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)....................................... Figure 12.2 Block Diagram of 8-Bit Timers (TMR_Y and TMR_X) ...
Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Output Timing of RESO signal............................................................................ Writing to TCNT and TCSR (WDT_0) ............................................................... Conflict between TCNT Write and Increment..................................................... Sample Circuit for Resetting System by RESO Signal........................................ Section 15 Serial Communication Interface (SCI and IrDA) Figure 15.
Figure 15.27 Sample Flowchart for Mode Transition during Reception................................... 410 Figure 15.28 Switching from SCK Pins to Port Pins ................................................................ 411 Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 411 2 Section 16 I C Bus Interface (IIC) (Optional) 2 Figure 16.1 Block Diagram of I C Bus Interface .................................................................... 2 Figure 16.
Figure 16.28 Figure 16.29 Figure 16.30 Figure 16.31 Figure 16.32 Figure 16.33 Figure 16.34 Figure 16.35 Figure 16.36 Figure 16.37 IRIC Setting Timing and SCL Control (3)........................................................... Block Diagram of Noise Canceler ....................................................................... Notes on Reading Master Receive Data...............................................................
Figure 19.5 Figure 19.6 Figure 19.7 Figure 19.8 Power-Down State Termination Timing.............................................................. SERIRQ Timing................................................................................................... Clock Start Request Timing................................................................................. HIRQ Flowchart (Example of Channel 1) ...........................................................
Figure 24.5 Figure 24.6 Figure 24.7 Figure 24.8 Figure 24.9 External Clock Input Timing ............................................................................... Timing of External Clock Output Stabilization Delay Time ............................... Subclock Input Timing ........................................................................................ Processing for X1 and X2 Pins ............................................................................
2 Figure 27.29 I C Bus Interface Input/Output Timing................................................................ 775 Figure 27.30 Host Interface (LPC) Timing ............................................................................... 775 Figure 27.31 Tester Measurement Condition............................................................................ 776 Appendix C Figure C.1 Figure C.2 Figure C.3 Package Dimensions Package Dimensions (FP-100B) ..................................................
Tables Section 1 Overview Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode ........................................................................................ 7 Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode ............... 12 Table 1.3 Pin Functions.......................................................................................................... 18 Section 2 CPU Table 2.1 Instruction Classification......................
Table 5.5 Table 5.6 Interrupt Response Times....................................................................................... 112 Number of States in Interrupt Handling Routine Execution Status........................ 112 Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... Table 6.2 Bus Specifications for Basic Bus Interface ............................................................ Table 6.
Table 10.4 Position of Pulse to Be Added to Basic Pulse (CFS = 1) ....................................... 256 Section 11 16-Bit Free-Running Timer (FRT) Table 11.1 Pin Configuration ................................................................................................... 261 Table 11.2 FRT Interrupt Sources............................................................................................ 279 Table 11.3 Switching of Internal Clock and FRC Operation ......................................
Table 15.9 SSR Status Flags and Receive Data Handling........................................................ 384 Table 15.10 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 404 Table 15.11 SCI Interrupt Sources ............................................................................................. 405 Section 16 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 16.7 Table 16.8 Table 16.9 Table 16.10 Table 16.
Section 20 D/A Converter Table 20.1 Pin Configuration ................................................................................................... 580 Table 20.2 D/A Channel Enable............................................................................................... 582 Section 21 A/D Converter Table 21.1 Pin Configuration ................................................................................................... 587 Table 21.2 Analog Input Channels and Corresponding ADDR Registers..
Table 27.8 Table 27.9 Table 27.10 Table 27.11 Table 27.12 Table 27.13 Table 27.14 Table 27.15 Table 27.16 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.17 Table 27.18 Table 27.19 Table 27.20 Table 27.21 Table 27.22 Table 27.22 Table 27.23 Table 27.23 Table 27.24 Table 27.25 Table 27.26 Table 27.27 Table 27.28 Table 27.29 Table 27.30 Timing of On-Chip Peripheral Modules (2) ........................................................... Keyboard Buffer Controller Timing.......
Rev. 3.
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory ROM Model ROM RAM F-ZTAT Version HD64F2161BV* 128 kbytes 4 kbytes HD64F2160BV* 64 kbytes 4 kbytes HD64F2141BV* 128 kbytes 4 kbytes HD64F2140BV* 64 kbytes 4 kbytes HD64F2145BV* 256 kbytes 8 kbytes HD64F2145B 256 kbytes 8 kbytes HD64F2148BV* 128 kbytes 4 kbytes HD64F2148B 128 kbytes 4 kbytes Remarks Under development Note: * 3-V version product • General I/O ports I/O pins: 74 (H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B) I/O pins: 114 (H
Section 1 Overview PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC Port 6 Port 2 Keyboard buffer controller × 3 channels 8-bit PWM PB7/D7/WUE7* PB6/D6/WUE6* PB5/D5/WUE5* PB4/D4/WUE4* PB3/D3/WUE3*/CS4 PB2/D2/WUE2*/CS3 PB1/D1/WUE1*/HIRQ4/LSCI* PB0/D0/WUE0*/HIRQ3/LSMI* Host interfaces (LPC*, XBS) 8-bit timer × 4 channels Timer connection 10-bit A/D converter SCI × 3 channels (IrDA × 1 channel) 8-bit D/A converter IIC × 2 channels Port 8 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P
Port A VSS VSS VSS VSS VCL VSS VCC VCC Section 1 Overview (Flash memory) Keyboard buffer controller × 3 channels 8-bit PWM 16-bit FRT P60/FTCI/CIN0/KIN0/HFBACKI/TMIX 14-bit PWM P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI Port 4 8-bit timer × 4 channels Timer connection P30/D8/HDB0/LAD0 Host interfaces (LPC, XBS) PB4/D4/WUE4 PB3/D3/WUE3/CS4 PB2/D2/WUE2/CS3 PB1/D1/WUE1/HIRQ4/LSCI PB0/D0/WUE0/HIRQ3/LSMI SCI × 3 channels (IrDA × 1 channel) Port 5 P34/D12/HDB4/LFRAME P33/D11/HDB3/LAD3 P32/D10/H
P42/TMRI0/SCK2/SDA1 P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P45/TMRI1/HIRQ12/CSYNCI P46/PWX0 P47/PWX1 PB6/D6/WUE6* PB7/D7/WUE7* VCC P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB4/D4/WUE4* PB5/D5/WUE5* VSS VSS P17/A7/PW7 Pin Arrangement P16/A6/PW6 1.3.1 P15/A5/PW5 Pin Arrangement and Functions P14/A4/PW4 1.
P12/A2/PW2 P11/A1/PW1 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC AVref P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P61/FTOA/CIN1/KIN1/VSYNCO P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P64/FTIC/CIN4/KIN4/CLAMPO P65/FTID/CIN5/KIN5 P63/FTIB/CIN3/KIN3/VFBACKI P66/FTOB/CIN6/KIN6/IRQ6 P67/TMOX/CIN7/KIN7/IRQ7 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3
Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview 1.3.3 Pin Functions Table 1.3 Pin Functions Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O Power VCC 59 1, 86 Input Power supply pin. Connect the pin to the system power supply. VCL 9 13 Input Power supply pin. Connect the pin to VCC. VCCB 4 36 Input The power supply for the port A input/output buffer. VSS 15, 70, 71, 7, 42, 95, Input 92 111, 139 Ground pin. Connect to the system power supply (0 V).
Section 1 Overview Pin No. FP-100B, TFP-100B TFP-144 I/O Type Symbol Address bus A23 to A16 10, 11, 20, 33, 34, 21, 30, 31, 35, 37, 47, 48 38, 39, 40, 41 A15 to A0 60 to 67, 72 to 79 Data bus Bus control Interrupt signals D15 to D8 89 to 82 Name and Function Output Address output pins when 16-Mbyte space is used. 96 to Output Address output pins 110, 112 128 to 121 Input/ output Bidirectional data bus for upper byte of 16-bit data.
Section 1 Overview Pin No. Type Symbol 16-bit free- FTCI running FTOA timer (FRT) FTOB FP-100B, TFP-100B TFP-144 I/O Name and Function 26 78 Input The counter clock input pin. 27 79 Output The output compare A output pin. 34 84 Output The output compare B output pin. FTIA 28 80 Input The input capture A input pin. FTIB 29 81 Input The input capture B input pin. FTIC 32 82 Input The input capture C input pin. FTID 33 83 Input The input capture D input pin.
Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O Keyboard buffer controller PS2AC PS2BC PS2CC 31 21 11 39 37 34 Input/ Keyboard buffer controller Output synchronization clock input/output pins. PS2AD PS2BD PS2CD 30 20 10 38 35 33 Input/ Keyboard buffer controller data Output input/output pins. HDB7 to HDB0 89 to 82 128 to 121 Input/ Bidirectional 8-bit bus for accessing Output XBS.
Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O Host interface (LPC) SERIRQ 89 Keyboard buffer controller A/D converter D/A converter 128 Name and Function Input/ Input/output pin for LPC serialized host Output interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to HIRQ12). LSCI, 90, 91, 93 LSMI, PME 119, 120, Input/ LPC auxiliary output pins. Functionally, 129 Output they are general I/O ports. GA20 94 130 Input/ A20 gate control signal output pin.
Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O A/D converter AVCC 37 76 Input D/A converter Name and Function The analog power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+3 V). AVref 36 77 Input The reference power supply pin for the A/D converter and D/A converter.
Section 1 Overview Pin No. FP-100B, TFP-100B TFP-144 I/O Name and Function Type Symbol I/O ports P52 to P50 12 to 14 14 to 16 Input/ Three input/output pins. Output (The output type of P52 is NMOS pushpull.) P67 to P60 35 to 32 29 to 26 85 to 78 Input/ Eight input/output pins. Output P77 to P70 45 to 38 75 to 68 Input P86 to P80 99 to 93 135 to 129 Input/ Seven input/output pins. Output (The output type of P86 is NMOS pushpull.
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 kbytes is possible.
Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) (a) Subroutine Branch SP CCR CCR* PC (16 bits) (b) Exception Handling Note: * Ignored when returning. Figure 2.2 Stack Structure in Normal Mode 2.2.
Section 2 CPU • Instruction set All instructions and addressing modes can be used. • Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4, Exception Handling.
Section 2 CPU • Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) (a) Subroutine Branch CCR SP PC (24 bits) (b) Exception Handling Figure 2.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI.
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.
Section 2 CPU 2.4.5 Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.
Section 2 CPU Data Type General Register Word data Rn Data Image 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) 1 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd SUB Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd 1 Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5 + → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
Section 2 CPU (1) Operation field only op NOP, RTS (2) Operation field and register fields op rm rn ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11.
Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 2.7.
Section 2 CPU Register Indirect with Pre-Decrement—@–ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.
Section 2 CPU 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don’t care Sign extension abs @aa:24 31 op 8 7 24 23 Don’t care abs 24 23 0 Don’t care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don’t care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request Program execution state End of bus request SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1.
Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5. 2.9.
Section 2 CPU Prior to executing BCLR: P47 P46 P45 P44 P43 P42 P41 P40 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 BCLR instruction executed: BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4.
Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). R5 R6 R5 + R4L Invalid H'FFFF R6 + R4L Rev. 3.
Section 2 CPU Rev. 3.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes. Table 3.
Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Bit Name Initial Value R/W Description 7 EXPE —* R/W* Extended Mode Enable Specifies extended mode. Fixed to 1 and cannot be modified in mode 1. Readable/writable and the initial value is 0 in mode 2 or 3.
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space.
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 2 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input.
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 7 IICS 0 R/W I C Extra Buffer Select 2 Specifies bits 7 to 4 of port A as output buffers similar to SLC and SDA. These pins are used to implement 2 an I C interface only by software. 0: PA7 to PA4 are normal input/output pins. 1: PA7 to PA4 are input/output pins enabling bus driving. 2 6 IICX1 0 R/W I C Transfer Rate Select 1 and 0 5 IICX0 0 R/W These bits control the IIC operation.
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 3 FLSHE 0 R/W Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87.
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Section 3 MCU Operating Modes 3.3.4 Pin Functions in Each Operating Mode Pin functions of ports 1 to 3, 9, A, and B depend on the operating mode. Table 3.2 shows pin functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 to 3.10 show the address map in each operating mode.
Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM On-chip ROM H'DFFF H'DFFF External address space H'E080 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF On-chip RAM H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00
Section 3 MCU Operating Modes Mode 1 Normal mode Extended mode with on-chip ROM disabled Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled External address space H'01FFFF External address space H'FFE080 H'FFE080 H'E080 Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 On-chip RAM On-chip RAM* On-chip RAM* External address space On-chip ROM On-chip ROM H'01FFFF H'020000 H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF0
Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM On-chip ROM H'DFFF H'DFFF External address space H'E080 H'E080 On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF On-chip RAM H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00
Section 3 MCU Operating Modes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled Mode 1 Normal mode Extended mode with on-chip ROM disabled External address space H'03FFFF External address space H'FFD080 H'FFD080 H'E080 On-chip RAM* External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 On-chip ROM On-chip ROM H'03FFFF H'040000 H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'000
Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM On-chip ROM H'DFFF H'DFFF External address space H'E080 H'E080 On-chip RAM On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'EFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00
Section 3 MCU Operating Modes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled Mode 1 Normal mode Extended mode with on-chip ROM disabled External address space H'03FFFF External address space H'FFD080 H'FFD080 External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 On-chip RAM On-chip RAM* On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF On-chip ROM On-chip ROM H'03FFFF H'04000
Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM On-chip ROM H'DFFF H'DFFF External address space H'E080 H'E080 On-chip RAM On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'EFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Int
Section 3 MCU Operating Modes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM enabled Mode 1 Normal mode Extended mode with on-chip ROM disabled External address space H'01FFFF External address space H'FFE080 H'FFE080 External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 On-chip RAM On-chip RAM* On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF On-chip ROM On-chip ROM H'01FFFF H'02000
Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM On-chip ROM H'DFFF H'DFFF External address space H'E080 H'E080 On-chip RAM On-chip RAM* H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF H'EFFF External address space Reserved area Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Int
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.
Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.
Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer.
Section 4 Exception Handling Vector fetch Internal Prefetch of first program processing instruction φ RES (1) Internal address bus (3) Internal read signal High Internal write signal Internal data bus (1) (2) (3) (4) (2) (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.1 Reset Sequence (Mode 3) 4.3.
Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1.
Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode SP CCR Advanced mode SP CCR CCR* PC (16 bits) PC (24 bits) Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 3.
Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.
Section 4 Exception Handling Rev. 3.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break.
Section 5 Interrupt Controller CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input IRQ input IRQ input ISR KIN input WUE input ISCR IER KMIMR WUEMR Interrupt request Vector number Priority check I, UI KIN and WUE input CCR Internal interrupt request SWDTEND to IBF13 ICR Interrupt controller Legend: ICR ISCR IER ISR KMIMR WUEMR SYSCR : Interrupt control register : IRQ sense control register : IRQ enable register : IRQ status register : Keyboard matrix interrupt mask register : Wake-up event inte
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O Function NMI Input Nonmaskable external interrupt IRQ7 to IRQ0 Input Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin.
Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested. Bit Bit Name Initial Value R/W Description 7 CMF 0 R Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1.
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. • BARA Bit Bit Name Initial Value R/W Description 7 to 0 A23 to A16 All 0 R/W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Section 5 Interrupt Controller 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 7 IRQ7E 0 R/W IRQn Enable (n = 7 to 0) 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W The IRQn interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W 5.3.
Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0).
Section 5 Interrupt Controller • WUEMRB* Bit Bit Name Initial Value R/W Description 7 WUEMR7 1 R/W Wake-Up Event Interrupt Mask 7 to 0 6 WUEMR6 1 R/W 5 WUEMR5 1 R/W These bits enable or disable a wake-up event input interrupt request (WUE7 to WUE0).
Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 IRQ6 internal signal KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8 IRQ6E IRQ6SC IRQ6 interrupt IRQ7 internal signal KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 Edge level selection enable/disable circuit IRQ7E IRQ7SC Edge level selection enable/disable circuit IRQ7 interrupt Figure 5.
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode.
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S Q IRQn interrupt request R IRQn input Note: n = 7 to 0 Clear signal Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored.
Section 5 Interrupt Controller 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Name Vector Normal Number Mode Advanced Mode TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use 68 69 70 71 H'0088 H'008A H'008C H'008E TMR_X, TMR_Y CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture X) 72 73 74 75 XBS IBF1 (IDR1 reception completion) IBF2 (IDR2 reception completion) IBF3 (IDR3 reception completion) IBF4 (IDR4 reception completion)
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.
Section 5 Interrupt Controller 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. • An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0.
Section 5 Interrupt Controller Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Section 5 Interrupt Controller Program excution state No Interrupt generated? Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes IRQ0 Yes No No IRQ0 No Yes IRQ1 No IRQ1 Yes Yes IFBFI3 IFBFI3 Yes Yes No I=0 I=0 Yes No UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 3.
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.
(2) (4) (3) (5) (7) (1) Internal data bus (1) (2) (4) Instruction prefetch (3) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times No.
Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Selection of a number of the above For details on interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller.
Section 5 Interrupt Controller Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See table 7.1 for the respective priority. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.
Section 5 Interrupt Controller 5.7 Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. 5.7.2 Block Diagram Figure 5.
Section 5 Interrupt Controller 5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed.
Section 5 Interrupt Controller (1) When a break address specified instruction is executed for one state in the program area and on-chip memory Vector fetch Save to stack Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Instruction Internal fetch operation φ H'0310 H'0312 H'0314 H'0316 Address bus NOP NOP execution execution H'0318 SP-2 NOP execution SP-4 H'0036 Interrupt exception handling Break request signal H'0310 H'0312 H'0314 H'03
Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.
Section 5 Interrupt Controller 5.8.5 IRQ Status Register (ISR) According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset to write 0. (n = 7 to 0) Rev. 3.
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters – CPU, and data transfer controller (DTC). 6.
Section 6 Bus Controller (BSC) External bus control signals Bus controller Internal control signals Bus mode signal Wait controller WAIT Internal data bus BCR WSCR CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev. 3.
Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Symbol I/O Function AS Output Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). IOS Output I/O select signal (when the IOSE bit in SYSCR is set to 1). RD Output Strobe signal indicating that the external address space is being read.
Section 6 Bus Controller (BSC) 6.3.1 Bus Control Register (BCR) BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin. Bit Bit Name Initial Value R/W Description 7 — 1 R/W Reserved This bit should not be written by 0. 6 ICIS0 1 R/W Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between bus cycles when the external write cycle follows the external read cycle.
Section 6 Bus Controller (BSC) 6.3.2 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces. The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 1 WC1 1 R/W Wait Count 1, 0 0 WC0 1 R/W Select the number of program wait states to be inserted when the external address space is accessed while the AST bit is set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted 6.4 Bus Control 6.4.
Section 6 Bus Controller (BSC) Table 6.2 shows the bus specifications for the basic bus interface of each area. Table 6.2 Bus Specifications for Basic Bus Interface Bus Specifications ABW AST WMS1 WMS0 WC1 0 0 — — 1 0 1 —* —* 0 0 Bus Width — — 16 2 0 — — 16 3 0 3 0 6.4.
Section 6 Bus Controller (BSC) RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. 6.4.4 I/O Select Signals The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 φ Address bus External addresses selected by IOS IOS Figure 6.
Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.2 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller (BSC) Upper data bus Lower data bus D15 D8 D7 D0 Byte size • Even address Byte size • Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.4 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus.
Section 6 Bus Controller (BSC) 6.5.3 Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space Rev. 3.
Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space Rev. 3.
Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev. 3.
Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.
Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Rev. 3.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.
Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin.
Section 6 Bus Controller (BSC) By program wait T1 T2 TW By WAIT pin TW TW T3 φ WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: ↓ shown in φ clock indicates the WAIT pin sampling timing. Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) Rev. 3.
Section 6 Bus Controller (BSC) 6.6 Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. 6.6.
Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Only lower address changes Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.4, Wait Control.
Section 6 Bus Controller (BSC) Bus cycle A φ T1 T2 T3 Bus cycle B T1 Bus cycle A T2 φ Address bus Address bus RD RD HWR, LWR HWR, LWR Data bus Data bus T1 T2 T3 Bus cycle B TI T1 T2 Data collision Long output floating time (b) Idle cycle insertion (a) No idle cycle insertion Figure 6.16 Examples of Idle Cycle Operation Table 6.5 shows the pin states in an idle cycle. Table 6.
Section 6 Bus Controller (BSC) 6.8 Bus Arbitration The bus controller has a bus arbiter that arbitrates bus master operations. There are two bus masters – the CPU and DTC – that perform read/write operations when they have possession of the bus. 6.8.1 Priority of Bus Masters Each bus master requests the bus by means of a bus request signal.
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1.
Section 7 Data Transfer Controller (DTC) Internal address bus CPU interrupt request Internal data bus Legend: : DTC mode register A, B MRA, MRB : DTC transfer count register A, B CRA, CRB : DTC source address register SAR : DTC destination register DAR DTCERA to DTCERE : DTC enable registers A to E : DTC vector register DTVECR Figure 7.1 Block Diagram of DTC Rev. 3.
Section 7 Data Transfer Controller (DTC) 7.2 Register Descriptions The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
Section 7 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 7 SM1 Undefined — Source Address Mode 1, 0 6 SM0 Undefined — These bits specify an SAR operation after a data transfer.
Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined — DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 7.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed.
Section 7 Data Transfer Controller (DTC) 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 at a reset and in hardware standby mode. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can always be written to this bit. 0 can be written to after reading 1 from this bit.
Section 7 Data Transfer Controller (DTC) 7.3 Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag in SCI_0.
Section 7 Data Transfer Controller (DTC) 7.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information.
Section 7 Data Transfer Controller (DTC) Table 7.
Section 7 Data Transfer Controller (DTC) 7.5 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode.
Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.2 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 7.
Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated.
Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.4 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored.
Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation.
Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller.
Section 7 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.
Section 7 Data Transfer Controller (DTC) Table 7.5 DTC Execution Status Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N: Block size (initial setting of CRAH and CRAL) Table 7.
Section 7 Data Transfer Controller (DTC) 7.6 Procedures for Using DTC 7.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 7 Data Transfer Controller (DTC) 7.7 Examples of Use of DTC 7.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 7 Data Transfer Controller (DTC) 7.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1.
Section 7 Data Transfer Controller (DTC) 7.8 Usage Notes 7.8.1 Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode cannot be specified. For details, refer to section 26, Power-Down Modes. 7.8.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM.
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview This LSI has ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7). For additional ports C to G in H8S/2160B and H8S/2161B, see section 8.13 Additional Overview for H8S/2160B and H8S/2161B. Table 8.1 is a summary of the port functions. The pins of each port also have other functions.
Section 8 I/O Ports Table 8.
Section 8 I/O Ports Port Description Port 4 General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, timer connection input/output, XBS host interrupt request output, SCI_2 input/output, IrDA interface input/output, and IIC_1 input/output pins Mode 1 Modes 2 and 3 (EXPE = 1) (EXPE = 0) P47/PWX1 P47/PWX1 P46/ PWX0 P46/PWX0 P45/TMRI1/CSYNCI P45/TMRI1/HIRQ12/ CSYNCI P44/TMO1/HSYNCO I/O Status P44/TMO1/HIRQ1/ HSYNCO P43/TMCI1/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD
Section 8 I/O Ports Port Description Port 8 General I/O port also functioning as interrupt input, SCI_1 input/output, XBS control input/output, LPC input/output, and IIC_1 input/output pins Port 9 General I/O port also functioning as extended data bus control input/output, IIC_0 input/output, subclock input, φ output, interrupt input, XBS control input, and A/D converter external trigger input pins Port A General I/O port also functioning as address output, key-sense interrupt input, extended A/D inp
Section 8 I/O Ports Port Description Port B General I/O port also functioning as wakeup event interrupt input, data bus input/output, XBS control input/output, and LPC input/output pins Note: * Mode 1 Modes 2 and 3 (EXPE = 1) (EXPE = 0) PB7/D7/WUE7* PB6/D6/WUE6* PB7/WUE7* PB6/WUE6* PB5/D5/WUE5* PB4/D4/WUE4* PB5/WUE5* PB4/WUE4* PB3/D3/WUE3* PB2/D2/WUE2* PB3/WUE3*/CS4 PB2/WUE2*/CS3 PB1/D1/WUE1* PB0/D0/WUE0* PB1/WUE1*/HIRQ4/ LSCI* PB0/WUE0*/HIRQ3/ LSMI* I/O Status On-chip input pullup MOSs No
Section 8 I/O Ports 8.2 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus and PWM output pins. Port 1 functions change according to the operating mode. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 8.2.
Section 8 I/O Ports 8.2.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read. 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 8.2.
Section 8 I/O Ports 8.2.4 Pin Functions • P17/A7/PW7 to P10/A0/PW0 The pin function is switched as shown below according to the combination of the OEn bit in PWOERA of PWM, the P1nDDR bit, and operating mode.
Section 8 I/O Ports 8.3 Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output function, 8-bit PWM output pins, and the timer connection output pin. Port 2 functions change according to the operating mode. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 pull-up MOS control register (P2PCR) 8.3.
Section 8 I/O Ports 8.3.2 Port 2 Data Register (P2DR) P2DR stores output data for port 2. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 8.
Section 8 I/O Ports 8.3.4 Pin Functions To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. • P27/A15/PW15/CBLANK The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the CBOE bit in TCONRO of timer connection, the OE15 bit in PWOERB of PWM, the P27DDR bit, and operating mode.
Section 8 I/O Ports • P23/A11/PW11, P22/A10/PW10, P21/A9/PW9, P20/A8/PW8 The pin function is switched as shown below according to the combination of the OEm bit in PWOERB of PWM, the P2nDDR bit, and operating mode.
Section 8 I/O Ports 8.4 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, XBS bidirectional data bus, and LPC input/output pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 pull-up MOS control register (P3PCR) 8.4.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis.
Section 8 I/O Ports 8.4.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit Bit Name Initial Value R/W Description 7 P37DR 0 R/W 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 8.4.
Section 8 I/O Ports 8.4.4 Pin Functions • P37/D15/HDB7/SERIRQ*, P36/D14/HDB6/LCLK*, P35/D13/HDB5/LRESET*, P34/D12/HDB4/LFRAME*, P33/D11/HDB3/LAD3*, P32/D10/HDB2/LAD2*, P31/D9/HDB1/LAD1*, P30/D8/HDB0/LAD0* The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LPC3E to LPC1E bits in HICR0 of host interface (LPC), the P3nDDR bit, and operating mode. Note: * Not supported by the H8S/2148B and H8S/2145B (5-V version).
Section 8 I/O Ports 8.5 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as PWMX output pins, TMR_0 and TMR_1 I/O pins, timer connection I/O pins, SCI_2 I/O pins, IrDA interface I/O pins, XBS output pins, and the IIC_1 I/O pin. The output type of P42 and SCK2 is NMOS push-pull output. The output type of SDA1 is NMOS open drain output. Port 4 pin functions are the same in all operating modes. Port 4 has the following registers.
Section 8 I/O Ports 8.5.2 Port 4 Data Register (P4DR) P4DR stores output data for port 4. Bit Bit Name Initial Value R/W Description 7 P47DR 0 R/W 6 P46DR 0 R/W 5 P45DR 0 R/W 4 P44DR 0 R/W If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read. 3 P43DR 0 R/W 2 P42DR 0 R/W 1 P41DR 0 R/W 0 P40DR 0 R/W 8.
Section 8 I/O Ports • P45/TMRI1/HIRQ12/CSYNCI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2 and the P45DDR bit. P45DDR 0 HI12E 0 0 1 P45 input pin P45 output pin HIRQ12 output pin Pin Function 1 TMRI1 input pin, CSYNCI input pin* Note: * When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. It can also be used as the CSYNCI input pin.
Section 8 I/O Ports • P42/TMRI0/SCK2/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC1, the CKE1 and CKE0 bits in SCR of SCI_2, the C/A bit in SMR of SCI_2, and the P42DDR bit.
Section 8 I/O Ports • P40/TMCI0/TxD2/IrTxD The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P40DDR bit. TE 0 P40DDR Pin Function 1 0 1 — P40 input pin P40 output pin TxD2/IrTxD output pin TMCI0 input pin* Note: 8.6 When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin is used as the TMCI0 input pin. * Port 5 Port 5 is a 3-bit I/O port.
Section 8 I/O Ports 8.6.2 Port 5 Data Register (P5DR) P5DR stores output data for port 5 pins. Bit Bit Name Initial Value R/W Description 7 to 3 — All 1 — Reserved 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W The initial value must not be changed. 8.6.3 If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read.
Section 8 I/O Ports • P51/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit. RE 0 P51DDR Pin Function 1 0 1 — P51 input pin P51 output pin RxD0 input pin • P50/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit. TE 0 P50DDR Pin Function 8.7 1 0 1 — P50 input pin P50 output pin TxD0 output pin Port 6 Port 6 is an 8-bit I/O port.
Section 8 I/O Ports 8.7.1 Port 6 Data Direction Register (P6DDR) P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 P67DDR 0 W 6 P66DDR 0 W The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0. 5 P65DDR 0 W 4 P64DDR 0 W 3 P63DDR 0 W 2 P62DDR 0 W 1 P61DDR 0 W 0 P60DDR 0 W 8.7.
Section 8 I/O Ports 8.7.3 Port 6 Pull-Up MOS Control Register (KMPCR) KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 KM7PCR 0 R/W 6 KM6PCR 0 R/W The input pull-up MOS is turned on when a KMPCR bit is set to 1 while the corresponding P6DDR bit is cleared to 0 (input port setting). 5 KM5PCR 0 R/W 4 KM4PCR 0 R/W 3 KM3PCR 0 R/W 2 KM2PCR 0 R/W 1 KM1PCR 0 R/W 0 KM0PCR 0 R/W 8.7.
Section 8 I/O Ports • P66/FTOB/CIN6/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit. OEB 0 P66DDR 0 1 P66 input pin P66 output pin Pin Function Note: * 1 — FTOB output pin IRQ6 input pin, KIN6 input pin, CIN6 input pin* This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 or CIN6 input pin.
Section 8 I/O Ports • P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P62DDR Pin Function 0 1 P62 input pin P62 output pin FTIA input pin, VSYNCI input pin, TMIY input pin, KIN2 input pin, CIN2 input pin* Note: * This pin can always be used as the FTIA, TMIY, KIN2, CIN2, or VSYNCI input pin. • P61/FTOA/CIN1/KIN1/VSYNCO The pin function is switched as shown below according to the combination of the OEA bit in TOCR of the FRT, the VOE bit in TCONRO of the timer connection function, and the P61DDR bit.
Section 8 I/O Ports 8.7.5 Port 6 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 8.5 summarizes the input pull-up MOS states. Table 8.
Section 8 I/O Ports 8.8.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit Bit Name Initial Value R/W 7 P77PIN R 6 P76PIN Undefined* Undefined* Undefined* Undefined* R Undefined* Undefined* R Undefined* Undefined* R 5 P75PIN 4 P74PIN 3 P73PIN 2 P72PIN 1 P71PIN 0 P70PIN Note: * 8.8.2 Description When a P7PIN read is performed, the pin states are always read.
Section 8 I/O Ports • P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0 Pin Function P75 to P70 input pins AN5 to AN0 input pin* Note: 8.9 This pin can always be used as the AN5 to AN0 input pins. * Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pin, XBS I/O pins, LPC I/O pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The output type of SCL1 is NMOS open drain output and direct bus driving is enabled.
Section 8 I/O Ports 8.9.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins (P86 to P80). Bit Bit Name Initial Value R/W 7 — 1 — Description Reserved The initial value must not be changed. 6 P86DR 0 R/W 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 8.9.3 If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states.
Section 8 I/O Ports • P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P85DDR bit. RE 0 P85DDR Pin Function Note: * 1 0 1 — P85 input pin P85 output pin IRQ4 input pin* RxD1 input pin When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin. • P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit.
Section 8 I/O Ports • P82/HIFSD/CLKRUN* 2 The pin function is switched as shown below according to the combination of the HI12E and SDE bits in SYSCR2, the LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPC3E to LPC1E All 0 HI12E 0 SDE — P82DDR Pin Function Notes: Not all 0 0* 1 0 1 1 0 1 0 1 — — 1 0* P82 input pin P82 output pin P82 input pin P82 output pin HIFSD input pin CLKRUN 2 I/O pin* The HIFSD input pin and CLKRUN I/O pin can only be used in mode 2 or 3 (EXPE = 0). 1.
Section 8 I/O Ports • P80/HA0/PME* 3 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the PMEE bit in HICR0, and the P80DDR bit. PMEE 0 HI12E 0 P80DDR 1 0 Pin Function P80 input pin 1 1 0* 1 0* — HA0 input pin* 2 3 PME input pin* * P80 output pin 2 1 PME output pin Notes: 1. When bit PMEE is set to 1 in HICR0, bits HI12E and P80DDR should be cleared to 0. 2. The HA0 input pin can only be used in mode 2 or 3 (EXPE = 0). 3.
Section 8 I/O Ports 8.10.1 Port 9 Data Direction Register (P9DDR) P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 P97DDR 0 W 6 P96DDR 1/0* W P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3).
Section 8 I/O Ports 8.10.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Bit Name Initial Value R/W Description 7 P97DR 0 R/W 6 P96DR Undefined* R 5 P95DR 0 R/W 4 P94DR 0 R/W 3 P93DR 0 R/W With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read.
Section 8 I/O Ports • P96/φ/EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR 0 EXCLE Pin Function 1 0 1 0 P96 input pin EXCL input pin φ output pin Note: When this pin is used as the EXCL input pin, P96DDR should be cleared to 0. • P95/AS/IOS/CS1 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, the HI12E bit in SYSCR2, and the P95DDR bit.
Section 8 I/O Ports • P93/RD/IOR The pin function is switched as shown below according to the combination of operating mode, the HI12E bit in SYSCR2, and the P93DDR bit.
Section 8 I/O Ports • P90/LWR/IRQ2/ADTRG/ECS2 The pin function is switched as shown below according to the combination of operating mode, the ABW bit in WSCR, the HI12E and CS2E bits in SYSCR2, the FGA20E bit in HICR, and the P90DDR bit.
Section 8 I/O Ports 8.11.1 Port A Data Direction Register (PADDR) PADDR specifies input or output for the pins of port A on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W In mode 1, 2 (EXPE = 0), or 3: 6 PA6DDR 0 W 5 PA5DDR 0 W The corresponding port A pins are output ports when PADDR bits are set to 1, and input ports when cleared to 0.
Section 8 I/O Ports 8.11.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit Bit Name Initial Value R/W Description 7 PA7PIN R 6 PA6PIN Undefined* Undefined* Undefined* Undefined* Reading PAPIN always returns the pin states. PAPIN has the same address as PADDR. If a write is performed, the port A settings will change.
Section 8 I/O Ports • PA6/A22/KIN14/CIN14/PS2CC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_2 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA6DDR bit.
Section 8 I/O Ports • PA4/A20/KIN12/CIN12/PS2BC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_1 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA4DDR bit.
Section 8 I/O Ports • PA2/A18/KIN10/CIN10/PS2AC The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCRH_0 of the keyboard buffer controller, the IOSE bit in SYSCR, and the PA2DDR bit.
Section 8 I/O Ports • PA0/A16/ KIN8/CIN8 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the PA0DDR bit. Operating Mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1) PA0DDR 0 1 0 IOSE — — — PA0 input pin PA0 output pin PA0 input pin Pin Function Note: 8.11.5 * 1 0 1 A16 output pin KIN8 input pin, CIN8 input pin* PA0 output pin This pin can always be used as the KIN8 or CIN8 input pin.
Section 8 I/O Ports 8.12 Port B Port B is an 8-bit I/O port. Port B pins also have XBS input/output pins, LPC input/output pins, wakeup event interrupt input pins, and a data bus input/output function. The pin functions depend on the operating mode. Port B has the following registers. • Port B data direction register (PBDDR) • Port B output data register (PBODR) • Port B input data register (PBPIN) 8.12.
Section 8 I/O Ports 8.12.2 Port B Output Data Register (PBODR) PBODR stores output data for port B. Bit Bit Name Initial Value R/W Description 7 PB7ODR 0 R/W 6 PB6ODR 0 R/W PBODR can always be read or written to, regardless of the contents of PBDDR. 5 PB5ODR 0 R/W 4 PB4ODR 0 R/W 3 PB3ODR 0 R/W 2 PB2ODR 0 R/W 1 PB1ODR 0 R/W 0 PB0ODR 0 R/W 8.12.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state.
Section 8 I/O Ports 8.12.4 Pin Functions 2 2 2 2 • PB7/D7/WUE7* , PB6/D6/WUE6* , PB5/D5/WUE5* , PB4/D4/WUE4* The pin function is switched as shown below according to the combination of the operating mode, the PBnDDR bit, and the ABW bit in WSCR. Operating Mode Mode 1 and Modes 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) ABW 0 PBnDDR — 0 1 Pin Function Dn I/O pin PBn input pin PBn output pin 1 — 0 1 PBn input pin 1 WUEn input pin* PBn output pin Notes: 1.
Section 8 I/O Ports Operating Mode Mode 1 and Modes 2, 3 (EXPE = 1) HI12E — CS3E — Modes 2, 3 (EXPE = 0) Either cleared to 0 1 1 ABW 0 PB2DDR — 0 1 1 0 — 1 — — Pin Function D2 I/O pin PB2 input pin PB2 output pin PB2 input pin PB2 output pin CS3 input pin WUE2 input pin* 1 Notes: 1. Except when used as a data bus pin, this pin can always be used as the WUE2 input pin. The CS3 input pin can only be used in mode 2 or 3 (EXPE = 0). 2.
Section 8 I/O Ports • PB0/D0/WUE0/HIRQ3/LSMI* 4 The pin function is switched as shown below according to the combination of the operating mode, the HI12E and CS3E bits in SYSCR2, the LSMIE bits in HICR0 of host interface (LPC), the ABW bit in WSCR, and the PB0DDR bit.
Section 8 I/O Ports 8.12.5 Port B Input Pull-Up MOS Port B has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 8.7 summarizes the input pull-up MOS states. Table 8.
Section 8 I/O Ports The output type on port G is NMOS push-pull output. Port G can be 5-V tolerant. When port G is used as an output pin, connect a pull-up resistor to the pin for raise an output highlevel voltage. Table 8.
Section 8 I/O Ports 8.14.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) PCDDR and PDDDR select input or output for the pins of port C and port D on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 PC7DDR 0 W 0: Port C pin is an input pin 6 PC6DDR 0 W 1: Port C pin is an output pin 5 PC5DDR 0 W 4 PC4DDR 0 W PCDDR has the same address as PCPIN, and if read, the port C pin states will be returned.
Section 8 I/O Ports 8.14.2 Port C and Port D Output Data Registers (PCODR, PDODR) PCODR and PDODR store output data for the pins on ports C and D. Bit Bit Name Initial Value R/W Description 7 PC7ODR 0 R/W 6 PC6ODR 0 R/W PCODR can always be read or written to, regardless of the contents of PCDDR.
Section 8 I/O Ports 8.14.3 Port C and Port D Input Data Registers (PCPIN, PDPIN) Reading PCPIN and PDPIN always returns the pin states. Bit Bit Name Initial Value R/W Description 7 PC7PIN R 6 PC6PIN Undefined* Undefined* Undefined* Undefined* PCPIN indicates the port C state. PCPIN has the same address as PCDDR. If a write is performed, the port C settings will change.
Section 8 I/O Ports 8.14.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) PCNOCR and PDNOCR specify the output driver type for pins on ports C and D which are configured as outputs on a bit-by-bit basis.
Section 8 I/O Ports 8.14.6 Input Pull-Up MOS in Ports C and D Port C and port D have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 8.9 is a summary of the input pull-up MOS states. Table 8.9 Input Pull-Up MOS States (Port C and port D) Mode Reset Hardware Standby Mode Software Standby Mode Other Operations 1 to 3 Off Off On/Off On/Off Legend: Off: Input pull-up MOS is always off.
Section 8 I/O Ports 8.15.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) PEDDR and PFDDR select input or output for the pins of port E and port F on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 PE7DDR 0 W 0: Port E pin is an input pin 6 PE6DDR 0 W 1: Port E pin is an output pin 5 PE5DDR 0 W 4 PE4DDR 0 W PEDDR has the same address as PEPIN, and if read, the port E pin states will be returned.
Section 8 I/O Ports 8.15.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data for the pins on ports E and F. Bit Bit Name Initial Value R/W Description 7 PE7ODR 0 R/W 6 PE6ODR 0 R/W PEODR can always be read or written to, regardless of the contents of PEDDR.
Section 8 I/O Ports 8.15.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN always returns the pin states. Bit Bit Name Initial Value R/W Description 7 PE7PIN R 6 PE6PIN Undefined* Undefined* Undefined* Undefined* PEPIN indicates the port E state. PEPIN has the same address as PEDDR. If a write is performed, the port E settings will change.
Section 8 I/O Ports 8.15.4 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR) PENOCR and PFNOCR specify the output driver type for pins on ports E and F which are configured as outputs on a bit-by-bit basis.
Section 8 I/O Ports 8.15.6 Input Pull-Up MOS in Ports E and F Port E and port F have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 8.10 is a summary of the input pull-up MOS states. Table 8.10 Input Pull-Up MOS States (Port E and port F) Mode Reset Hardware Standby Mode Software Standby Mode Other Operations 1 to 3 Off Off On/Off On/Off Legend: Off: Input pull-up MOS is always off.
Section 8 I/O Ports 8.16.1 Port G Data Direction Register (PGDDR) PGDDR selects input or output for the pins of port G on a bit-by-bit basis. Bit Bit Name Initial Value R/W Description 7 PG7DDR 0 W 0: Port G pin is an input pin 6 PG6DDR 0 W 1: Port G pin is an output pin 5 PG5DDR 0 W 4 PG4DDR 0 W PGDDR has the same address as PGPIN, and if read, the port G pin states will be returned. 3 PG3DDR 0 W 2 PG2DDR 0 W 1 PG1DDR 0 W 0 PG0DDR 0 W 8.16.
Section 8 I/O Ports 8.16.3 Port G Input Data Register (PGPIN) Reading PGPIN always returns the pin states. Bit Bit Name Initial Value R/W Description 7 PG7PIN R 6 PG6PIN Undefined* Undefined* Undefined* Undefined* PGPIN indicates the port G state. PGPIN has the same address as PGDDR. If a write is performed, the port G settings will change. R Undefined* Undefined* R Undefined* Undefined* R 5 PG5PIN 4 PG4PIN 3 PG3PIN 2 PG2PIN 1 PG1PIN 0 PG0PIN Note: 8.16.
Section 8 I/O Ports 8.16.5 Pin Functions DDR 0 NOCR — ODR 0 1 0 1 1 0 1 0 1 ON OFF Vss-side N-ch. driver OFF ON OFF Vcc-side N-ch. driver OFF OFF ON Pin function Input pin Rev. 3.
Section 9 8-Bit PWM Timer (PWM) Section 9 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. 9.
Section 9 8-Bit PWM Timer (PWM) Figure 9.1 shows a block diagram of the PWM timer.
Section 9 8-Bit PWM Timer (PWM) 9.2 Input/Output Pin Table 9.1 shows the PWM output pins. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output 15 to 0 PW15 to PW0 Output PWM timer pulse output 15 to 0 9.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR).
Section 9 8-Bit PWM Timer (PWM) 9.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Bit Name Initial Value R/W Description 7 PWCKE 0 R/W PWM Clock Enable 6 PWCKS 0 R/W PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 9.2.
Section 9 8-Bit PWM Timer (PWM) Bit Bit Name Initial Value R/W Description 3 RS3 0 R/W Register Select 2 RS2 0 R/W These bits select the PWM data register.
Section 9 8-Bit PWM Timer (PWM) Resolution, PWM Conversion Period and Carrier Frequency when φ = 10 MHz Table 9.3 Internal Clock Frequency Resolution PWM Conversion Period Carrier Frequency φ 100 ns 25.6 µs 625 kHz φ/2 200 ns 51.2 µs 312.5 kHz φ/4 400 ns 102.4 µs 156.3 kHz φ/8 800 ns 204.8 µs 78.1 kHz φ/16 1600 ns 409.6 µs 39.1 kHz 9.3.2 PWM Data Registers (PWDR0 to PWDR15) PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers.
Section 9 8-Bit PWM Timer (PWM) • PWDPRB Bit Bit Name Initial Value R/W Description 7 OS15 0 R/W Output Select 15 to 8 6 OS14 0 R/W 5 OS13 0 R/W These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 4 OS12 0 R/W 3 OS11 0 R/W 2 OS10 0 R/W 1 OS9 0 R/W 0 OS8 0 R/W 9.3.
Section 9 8-Bit PWM Timer (PWM) • PWOERB Bit Bit Name Initial Value R/W Description 7 OE15 0 R/W Output Enable 15 to 8 6 OE14 0 R/W 5 OE13 0 R/W 4 OE12 0 R/W These bits, together with P2DDR, specify the P2n/PWn pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8.
Section 9 8-Bit PWM Timer (PWM) 9.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Upper 4 Bits 0000 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses.
Section 9 8-Bit PWM Timer (PWM) the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. Table 9.5 Lower 4 Bits Position of Pulses Added to Basic Pulses Basic Pulse No.
Section 9 8-Bit PWM Timer (PWM) 9.5 Usage Note 9.5.1 Module Stop Mode Setting PWM operation can be enabled or disabled using the module stop control register. The initial setting is for PWM operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.
Section 9 8-Bit PWM Timer (PWM) Rev. 3.
Section 10 14-Bit PWM Timer (PWMX) Section 10 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 10.1 Features • Division of pulse into multiple base cycles to reduce ripple • Two resolution settings The resolution can be set equal to one or two system clock cycles.
Section 10 14-Bit PWM Timer (PWMX) 10.2 Input/Output Pins Table 10.1 lists the PWM (D/A) module input and output pins. Table 10.1 Pin Configuration Name Abbreviation I/O Function PWM output pin X0 PWX0 Output PWM output of PWMX channel A PWM output pin X1 PWX1 Output PWM output of PWMX channel B 10.3 Register Descriptions The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the same addresses with other registers.
Section 10 14-Bit PWM Timer (PWMX) 10.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits.
Section 10 14-Bit PWM Timer (PWMX) 10.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register (TEMP). For details, refer to section 10.4, Bus Master Interface.
Section 10 14-Bit PWM Timer (PWMX) • DADRB Bit Bit Name Initial Value R/W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D/A Data 13 to 0 These bits set a digital value to be converted to an analog value.
Section 10 14-Bit PWM Timer (PWMX) 10.3.3 PWM (D/A) Control Register (DACR) DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed. Bit Bit Name Initial Value R/W Description 7 TEST 0 R/W Test Mode Selects test mode, which is used in testing this LSI. Normally this bit should be cleared to 0.
Section 10 14-Bit PWM Timer (PWMX) Bit Bit Name Initial Value R/W Description 2 OEA 0 R/W Output Enable A Enables or disables output on PWM (D/A) channel A. 0: PWM (D/A) channel A output (at the PWX0 pin) is disabled 1: PWM (D/A) channel A output (at the PWX0 pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWM (D/A) output. 0: Direct PWM (D/A) output 1: Inverted PWM (D/A) output 0 CKS 0 R/W Clock Select Selects the PWM (D/A) resolution.
Section 10 14-Bit PWM Timer (PWMX) 10.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. Write: When the upper byte is written to, the upper-byte write data is stored in TEMP.
Section 10 14-Bit PWM Timer (PWMX) 10.5 Operation A PWM waveform like the one shown in figure 10.2 is output from the PWMX pin. The value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 10.3 and 10.
Section 10 14-Bit PWM Timer (PWMX) Table 10.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Table 10.3 Settings and Operation (Examples when φ = 10 MHz) Resolution Base Conversion CKS T CFS Cycle Cycle (µs) (µs) (µs) 0 0.1 0 1 1 0.2 0 6.4 1638.4 1. Always low (or high) (DADR = H'0001 to H'03FD) 2.
Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tL2 tf63 tL3 tL63 tf64 tL64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) × 256] Figure 10.3 Output Waveform (OS = 0, DADR Corresponds to TL) Rev.
Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tf256 tH255 tH256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf63 tH2 tH3 tf64 tH63 tH64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) × 256] Figure 10.
Section 10 14-Bit PWM Timer (PWMX) Since the value of the following six bits is B’0000 01, the additional pulse is output at the position of basic pulse No. 63 as shown in table 10.4. Only 1/256 × (T) of the additional pulse is added to the basic pulse. One conversion cycle Basic cycle Basic cycle Basic cycle No.0 No.1 No.63 Basic pulse High width: 2/256 × (T) Additional pulse output position Basic pulse 2/256 × (T) Additional pulse 1/256 × (T) Figure 10.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lower 6 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0
Section 10 14-Bit PWM Timer (PWMX) 10.6 Usage Note 10.6.1 Module Stop Mode Setting PWMX operation can be enabled or disabled using the module stop control register. The initial setting is for PWMX operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.
Section 10 14-Bit PWM Timer (PWMX) Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) Section 11 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 11.1 Features • Selection of four clock sources One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be selected (enabling use as an external event counter).
Section 11 16-Bit Free-Running Timer (FRT) Figure 11.1 shows a block diagram of the FRT.
Section 11 16-Bit Free-Running Timer (FRT) 11.2 Input/Output Pins Table 11.1 lists the FRT input and output pins. Table 11.
Section 11 16-Bit Free-Running Timer (FRT) 11.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 11.3.
Section 11 16-Bit Free-Running Timer (FRT) 11.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A.
Section 11 16-Bit Free-Running Timer (FRT) 11.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Value R/W Description 7 ICIAE 0 R/W Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Section 11 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value R/W Description 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Section 11 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value R/W Description 6 ICFB 0 R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. Only 0 can be written to this bit to clear the flag.
Section 11 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value R/W Description 3 OCFA 0 R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value.
Section 11 16-Bit Free-Running Timer (FRT) 11.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Bit Name Initial Value R/W Description 7 IEDGA 0 R/W Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA).
Section 11 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1, 0 0 CKS0 0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 11.3.
Section 11 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value R/W Description 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA).
Section 11 16-Bit Free-Running Timer (FRT) 11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.2 Example of Pulse Output Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) 11.5 Operation Timing 11.5.1 FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ). φ Internal clock FRC input clock FRC N–1 N N+1 Figure 11.
Section 11 16-Bit Free-Running Timer (FRT) 11.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A.
Section 11 16-Bit Free-Running Timer (FRT) 11.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected. φ Input capture input pin Input capture signal Figure 11.
Section 11 16-Bit Free-Running Timer (FRT) φ FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 11.9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal.
Section 11 16-Bit Free-Running Timer (FRT) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag. φ Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 11.
Section 11 16-Bit Free-Running Timer (FRT) φ FRC N OCRA, OCRB N+1 N Compare-match signal OCFA, OCFB Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 11.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of setting the OVF flag. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Timing of Overflow Flag (OVF) Setting Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) 11.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 11.14 shows the OCRA write timing. φ FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 11.14 OCRA Automatic Addition Timing 11.5.
Section 11 16-Bit Free-Running Timer (FRT) φ FRC N ICRD + OCRDM × 2 N+1 N Compare-match signal Input capture mask signal Figure 11.16 Timing of Input Capture Mask Signal Clearing 11.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts.
Section 11 16-Bit Free-Running Timer (FRT) 11.7 Usage Notes 11.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.17 FRC Write-Clear Conflict Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) 11.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.18 FRC Write-Increment Conflict Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) 11.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict.
Section 11 16-Bit Free-Running Timer (FRT) Write cycle of OCRAR/OCRAF T1 T2 φ Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Compare-match signal Old data New data Disabled FRC N OCRA N N+1 Automatic addition is not performed because compare-match signals are disabled. Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) 11.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 11.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ).
Section 11 16-Bit Free-Running Timer (FRT) No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: 11.7.5 * Generated on the assumption that the switchover is a falling edge; FRC is incremented.
Section 11 16-Bit Free-Running Timer (FRT) Rev. 3.
Section 12 8-Bit Timer (TMR) Section 12 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can count external events, and can also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Section 12 8-Bit Timer (TMR) Figures 12.1 and 12.2 show block diagrams of the 8-bit timer module. TMR_X and TMR_Y have a similar configuration, but cannot be cascaded. TMR_X also has an input capture function. For details, see section 13, Timer Connection.
Section 12 8-Bit Timer (TMR) External clock sources Internal clock sources TMCIY TMCIX TMR_X φ φ/2 φ/4 TMR_Y φ/4 φ/256 φ/2048 Clock X Clock Y Clock select Compare-match AX Compare-match AY Overflow X Overflow Y TCORA_Y TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Clear Y Compare- match BX TMRIY IVG signal Comparator B_Y Comparator B_X TCORB_Y TCORB_X Compare-match BY Internal bus Clear X Control logic TMOX TMRIX Input capture TICRR TICRF TICR Compare-match C Comparator C +
Section 12 8-Bit Timer (TMR) 12.2 Input/Output Pins Table 12.1 summarizes the input and output pins of the TMR. Table 12.
Section 12 8-Bit Timer (TMR) 12.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR.
Section 12 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. Note that a CMIB interrupt is not generated by TMR_X, regardless of the CMIEB value.
Section 12 8-Bit Timer (TMR) Table 12.
Section 12 8-Bit Timer (TMR) 12.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output.
Section 12 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3, 2 2 OS2 0 R/W These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 OS1 0 R/W Output Select 1, 0 0 OS0 0 R/W These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0.
Section 12 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W 5 OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 — 1 R Reserved This bit is always read as 1 and cannot be modified. 3 OS3 0 R/W Output Select 3, 2 2 OS2 0 R/W These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1.
Section 12 8-Bit Timer (TMR) • TCSR_Y Bit 7 Bit Name Initial Value R/W CMFB 0 Description 1 R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing conditions] 6 CMFA 0 • Read CMFB when CMFB = 1, then write 0 in CMFB • When the DTC is activated by a CMIB interrupt R/(W)* Compare-Match Flag A 1 [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing conditions] 5 OVF 0 • Read CMFA when CMFA = 1, then write 0 in CMFA • When
Section 12 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3, 2 2 OS2 0 R/W 2 These bits specify how the TMOY pin* output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 OS1 0 R/W Output Select 1, 0 0 OS0 0 R/W 2 These bits specify how the TMOY pin* output level is to be changed by compare-match A of TCORA_Y and TCNT_Y.
Section 12 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W 5 OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] 4 ICF 0 Read OVF when OVF = 1, then write 0 in OVF * R/(W) Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order, after the ICST bit in TCONRI of the timer connection is set to 1 [Clearing condition] Read ICF when ICF = 1, then write 0 in
Section 12 8-Bit Timer (TMR) 12.3.6 Input Capture Register (TICR) TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the external reset input. TICR cannot be directly accessed by the CPU. The TICR function is used for the timer connection. For details, refer to section 13, Timer Connection. 12.3.7 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT.
Section 12 8-Bit Timer (TMR) 12.4 Operation 12.4.1 Pulse Output Figure 12.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB.
Section 12 8-Bit Timer (TMR) 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges. The counter will not increment correctly if the pulse width is less than these values.
Section 12 8-Bit Timer (TMR) 12.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 12.6 shows the timing of CMF flag setting.
Section 12 8-Bit Timer (TMR) 12.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a compare-match. φ Compare-match signal TCNT N H'00 Figure 12.8 Timing of Counter Clear by Compare-Match 12.5.
Section 12 8-Bit Timer (TMR) 12.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 12.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00 Overflow signal OVF Figure 12.10 Timing of OVF Flag Setting 12.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded.
Section 12 8-Bit Timer (TMR) Counter Clear Specification: • If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. • The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently.
Section 12 8-Bit Timer (TMR) Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture operation. φ TMRIX Input capture signal TCNTX n TICRR M TICRF m n+1 n N N+1 n m N Figure 12.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock (φ) cycle. Figure 12.12 shows the timing of this operation.
Section 12 8-Bit Timer (TMR) Selection of Input Capture Signal Input: Input capture input signal of TMR_X (TMRIX) is switched according to the setting of the bits in TCONRI of the timer connection. Input capture signal selections are shown in figure 12.13 and table 12.3. For details, see section 13.3.1, Timer Connection Register I (TCONRI). TMR_X TMIX pin Polarity inversion TMRI1 pin Polarity inversion TMCI1 pin Polarity inversion HFINV, HIINV Signal selector TMRIX SIMOD1, SIMOD0 ICST Figure 12.
Section 12 8-Bit Timer (TMR) 12.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate an ICIX interrupt. Table 12.4 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as DTC activation interrupt sources. Table 12.
Section 12 8-Bit Timer (TMR) 12.9 Usage Notes 12.9.1 Conflict between TCNT Write and Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 12.14, clearing takes priority, so that the counter is cleared and the write is not performed. TCNT write cycle by CPU T1 T2 φ TCNT address Address Internal write signal TCNT input clock TCNT N H'00 Figure 12.14 Conflict between TCNT Write and Clear Rev. 3.
Section 12 8-Bit Timer (TMR) 12.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 12.15, the write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 φ TCNT address Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.15 Conflict between TCNT Write and Increment Rev. 3.
Section 12 8-Bit Timer (TMR) 12.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
Section 12 8-Bit Timer (TMR) 12.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.5. Table 12.5 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.9.
Section 12 8-Bit Timer (TMR) Table 12.6 Switching of Internal Clocks and TCNT Operation No.
Section 12 8-Bit Timer (TMR) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. 12.9.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
Section 12 8-Bit Timer (TMR) Rev. 3.
Section 13 Timer Connection Section 13 Timer Connection This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. 13.1 Features • Five input pins and four output pins, all of which can be designated for phase inversion. Positive logic is assumed for all signals used within the timer connection facility.
Rev. 3.00 Mar 21, 2006 page 318 of 788 REJ09B0300-0300 Figure 13.
Section 13 Timer Connection 13.2 Input/Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.
Section 13 Timer Connection 13.3.1 Timer Connection Register I (TCONRI) TCONRI controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. Bit Bit Name Initial Value R/W Description 7 SIMOD1 0 R/W Input Synchronization Mode Select 1, 0 6 SIMOD0 0 R/W These bits select the signal source of the IHI and IVI signals.
Section 13 Timer Connection Bit Bit Name Initial Value R/W Description 4 ICST 0 R/W Input Capture Start Bit The TMR_X external reset input (TMRIX) is connected to the IHI signal. TMR_X has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit.
Section 13 Timer Connection Bit Bit Name Initial Value R/W Description 3 HFINV 0 R/W Input Synchronization Signal Inversion 2 VFINV 0 R/W 1 HIINV 0 R/W 0 VIINV 0 R/W These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal (HSYNCI), composite synchronization signal (CSYNCI), and the vertical synchronization signal (VSYNCI).
Section 13 Timer Connection 13.3.2 Timer Connection Register O (TCONRO) TCONRO controls output signal output, phase inversion, etc. Bit Bit Name Initial Value R/W Description 7 HOE 0 R/W Output Enable 6 VOE 0 R/W 5 CLOE 0 R/W 4 CBOE 0 R/W These bits control enabling/disabling of output of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK).
Section 13 Timer Connection Bit Bit Name Initial Value R/W Description 3 HOINV 0 R/W Output Synchronization Signal Inversion 2 VOINV 0 R/W 1 CLOINV 0 R/W 0 CBOINV 0 R/W These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO), and the blanking waveform (CBLANK).
Section 13 Timer Connection 13.3.3 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers, and the synchronization signal output signal source and generation method. Bit Bit Name Initial Value R/W Description 7 TMRX/Y 0 R/W TMR_X/TMR_Y Access Select For details, see table 13.3.
Section 13 Timer Connection Bit Bit Name Initial Value R/W Description 3 VOMOD1 0 R/W Vertical Synchronization Output Mode Select 1, 0 2 VOMOD0 0 R/W These bits select the signal source and generation method for the IVO signal.
Section 13 Timer Connection 13.3.4 Edge Sense Register (SEDGR) SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH modification, and determines the phase of the IVI and IHI signals. Bit 7 Bit Name VEDG Initial Value R/W Description 0 R/(W)* VSYNCI Edge 1 Detects a rising edge on the VSYNCI pin.
Section 13 Timer Connection Bit 3 Bit Name VFEDG Initial Value R/W Description 0 R/(W)* VFBACKI Edge 1 Detects a rising edge on the VFBACKI pin. [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] 2 PREQF 0 When a rising edge is detected on the VFBACKI pin 1 * R/(W) Pre-Equalization Flag Detects the occurrence of an IHI signal 2fH modification condition.
Section 13 Timer Connection 13.4 Operation 13.4.1 PWM Decoding (PDC Signal Generation) The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal. The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal).
Section 13 Timer Connection IHI signal is tested at compare-match IHI signal PDC signal TCNT TCORB (threshold) Counter reset caused by IHI signal Counter clear caused by TCNT overflow At the 2nd compare-match, IHI signal is not tested Figure 13.2 Timing Chart for PWM Decoding 13.4.
Section 13 Timer Connection contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TCR settings of TMR_X are the same as those in table 13.4. The clamp waveform timing charts are shown in figures 13.3 and 13.4.
Section 13 Timer Connection 13.4.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR_1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR_1 can be cleared by a rising edge of the inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with the IVI signal. This enables period measurement to be carried out efficiently.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.4.4 2fH Modification of IHI Signal By using the timer connection facility and FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection 13.4.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection 13.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection facility, FRT, and TMR_Y, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR OCRA FRC 6 system clocks 6 system clocks 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart Rev. 3.
Section 13 Timer Connection 13.4.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The HSYNCO output modes are shown in table 13.10. Table 13.
Section 13 Timer Connection 13.4.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The VSYNCO output modes are shown in table 13.11. Table 13.
Section 13 Timer Connection Mode IVI Signal IVO Signal Meaning of IVO Signal Separate mode VSYNCI input IVI signal (without fall modification or IHI synchronization) VSYNCI input (vertical synchronization signal) is output directly IVI signal (without fall modification, with IHI synchronization) Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) IVI signal (with fall modification, without IHI synchronization) VSY
Section 13 Timer Connection 13.5 Usage Note 13.5.1 Module Stop Mode Setting Timer connection operation can be enabled or disabled using the module stop control register. The initial setting is for timer connection operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 26, Power-Down Modes. Rev. 3.
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 14 Watchdog Timer (WDT) Internal NMI (Interrupt request signal*2) Interrupt control Overflow Clock Clock selection Reset control *1 RESO signall Internal reset signal*1 TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal bus WOVI0 (Interrupt request signal) TCSR_0 Bus interface Module bus WDT_0 Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Overflow Clock φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock selecti
Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Symbol I/O Function Reset output pin RESO Output Outputs the counter overflow signal in watchdog timer mode Input Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin 14.3 Register Descriptions The WDT has the following registers.
Section 14 Watchdog Timer (WDT) 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit 7 Initial Bit Name Value R/W OVF 1 R/(W)* Overflow Flag 0 Description Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to. The overflow frequency for φ = 10 MHz is enclosed in parentheses. 000: φ/2 (frequency: 51.2 µs) 001: φ/64 (frequency: 1.64 ms) 010: φ/128 (frequency: 3.28 ms) 011: φ/512 (frequency: 13.1 ms) 100: φ/2048 (frequency: 52.4 ms) 101: φ/8192 (frequency: 209.7 ms) 110: φ/32768 (frequency: 0.84 s) 111: φ/131072 (frequency: 3.
Section 14 Watchdog Timer (WDT) • TCSR_1 Bit 7 Bit Name Initial Value R/W OVF 0 Description R/(W)*1 Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow cycle for φ = 10 MHz and φSUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 51.2 µs) 001: φ/64 (frequency: 1.64 ms) 010: φ/128 (frequency: 3.28 ms) 011: φ/512 (frequency: 13.1 ms) 100: φ/2048 (frequency: 52.4 ms) 101: φ/8192 (frequency: 209.
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally.
Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT OVF = 1* RESO and internal reset signals generated WT/IT = 1 Write H'00 to TME = 1 TCNT RESO signal 132 system clocks Internal reset signal 518 system clocks Legend: WT/IT : Timer mode select bit TME : Timer enable bit OVF : Overflow flag Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 14.
Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 14.4.
Section 14 Watchdog Timer (WDT) RESO Signal Output Timing 14.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 14.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal 132 states 518 states Internal reset signal Figure 14.5 Output Timing of RESO signal 14.
Section 14 Watchdog Timer (WDT) 14.6 Usage Notes 14.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address.
Section 14 Watchdog Timer (WDT) 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.7 Conflict between TCNT Write and Increment 14.6.
Section 14 Watchdog Timer (WDT) 14.6.5 System Reset by RESO Signal Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 14.8. This LSI Reset input Reset signal for entire system RES RESO Figure 14.8 Sample Circuit for Resetting System by RESO Signal 14.6.
Section 15 Serial Communication Interface (SCI and IrDA) Section 15 Serial Communication Interface (SCI and IrDA) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Section 15 Serial Communication Interface (SCI and IrDA) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors • Serial data communication with other LSIs that have the clock synchronized communication function A block diagram of the SCI is shown in figure 15.1.
Section 15 Serial Communication Interface (SCI and IrDA) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel Symbol* Input/Output Function 0 SCK0 Input/Output Channel 0 clock input/output 1 2 Note: 15.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
Section 15 Serial Communication Interface (SCI and IrDA) Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 R/W Clock Select 1,0 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator.
Section 15 Serial Communication Interface (SCI and IrDA) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 15 Serial Communication Interface (SCI and IrDA) Bit Bit Name Initial Value R/W Description 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Bit Bit Name Initial Value R/W Description 7 to — All 1 R Reserved 4 3 These bits are always read as 1 and cannot be modified. SDIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times.
Section 15 Serial Communication Interface (SCI and IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.
Section 15 Serial Communication Interface (SCI and IrDA) Operating Frequency φ (MHz) 6 6.144 7.3728 8 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.
Section 15 Serial Communication Interface (SCI and IrDA) Operating Frequency φ (MHz) 14 14.7456 16 17.2032 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.
Section 15 Serial Communication Interface (SCI and IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 9.8304 307200 0 0 2.097152 65536 0 0 10 312500 0 0 2.4576 76800 0 0 12 375000 0 0 3 93750 0 0 12.288 384000 0 0 3.6864 115200 0 0 14 437500 0 0 4 125000 0 0 14.7456 460800 0 0 4.9152 153600 0 0 16 500000 0 0 5 156250 0 0 17.
Section 15 Serial Communication Interface (SCI and IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 2 4 N n N 8 10 16 n N n N n N 20 n N 110 3 70 — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 — — 1k 1 124 1 249 2 124 — — 2 249 — — 2.
Section 15 Serial Communication Interface (SCI and IrDA) 15.3.10 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the functions of the SCI and A/D converter. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies SCI_2 I/O pins for either normal SCI or IrDA.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.1 Data Transfer Format Table 15.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function. Table 15.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface (SCI and IrDA) [1] Initialization Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI and IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 15 Serial Communication Interface (SCI and IrDA) Table 15.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flow chart for serial data reception. Table 15.
Section 15 Serial Communication Interface (SCI and IrDA) Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0.
Section 15 Serial Communication Interface (SCI and IrDA) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Flowchart (2) Rev. 3.
Section 15 Serial Communication Interface (SCI and IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface (SCI and IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB = 1) ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
Section 15 Serial Communication Interface (SCI and IrDA) Initialization [1] Start transmission Read TDRE flag in SSR [2] No [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI and IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.
Section 15 Serial Communication Interface (SCI and IrDA) Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start reception Set MPIE bit in SCR to 1 [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 15 Serial Communication Interface (SCI and IrDA) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.
Section 15 Serial Communication Interface (SCI and IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Section 15 Serial Communication Interface (SCI and IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI and IrDA) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
Section 15 Serial Communication Interface (SCI and IrDA) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode Rev. 3.
Section 15 Serial Communication Interface (SCI and IrDA) [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI and IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2.
Section 15 Serial Communication Interface (SCI and IrDA) Initialization [1] Start reception [2] Read ORER flag in SSR Yes ORER = 1 [3] No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI and IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Section 15 Serial Communication Interface (SCI and IrDA) Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI and IrDA) 15.7 IrDA Operation IrDA operation can be used with SCI_2. Figure 15.21 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in KBCOMP, the TxD2 and RxD2 pins in SCI_2 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins).
Section 15 Serial Communication Interface (SCI and IrDA) Transmission: During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.22). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in KBCOMP. The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.
Section 15 Serial Communication Interface (SCI and IrDA) High-Level Pulse Width Selection: Table 15.10 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.10 IrCKS2 to IrCKS0 Bit Settings Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.
Section 15 Serial Communication Interface (SCI and IrDA) 15.8 Interrupt Sources Table 15.11 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated.
Section 15 Serial Communication Interface (SCI and IrDA) 15.9 15.9.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 26, Power-Down Modes. 15.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly.
Section 15 Serial Communication Interface (SCI and IrDA) 15.9.6 Restrictions on Using DTC When an external clock source is used as a synchronization clock, update TDR by the DTC or RFU and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 15.23). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source.
Section 15 Serial Communication Interface (SCI and IrDA) Reception: Before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.
Section 15 Serial Communication Interface (SCI and IrDA) Transmission start Transition to Software standby Transmission end software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start Stop Port input/output SCI TxD output Port Port High output SCI TxD output Figure 15.
Section 15 Serial Communication Interface (SCI and IrDA) Reception Read RDRF flag in SSR RDRF = 1 No [1] [1] Data being received will be invalid. Yes Read receive data in RDR [2] Module stop, watch, sub-active, and subsleep modes are included. RE = 0 [2] Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? No Yes Initialization RE = 1 Start reception Figure 15.27 Sample Flowchart for Mode Transition during Reception Rev. 3.
Section 15 Serial Communication Interface (SCI and IrDA) 15.9.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.28. Low pulse of half a cycle SCK/Port 1. Transmission end Data Bit 6 4. Low pulse output Bit 7 2. TE = 0 TE 3. C/A = 0 C/A CKE1 CKE0 Figure 15.
Section 15 Serial Communication Interface (SCI and IrDA) Rev. 3.
2 Section 16 I C Bus Interface (IIC) (Optional) 2 Section 16 I C Bus Interface (IIC) (Optional) 2 The I C bus interface is provided as an optional function. Note the following point when using this optional function. • Although the product type name is identical, please contact Renesas before using this optional function on an F-ZTAT version product. 2 2 This LSI has a two-channel I C bus interface.
2 Section 16 I C Bus Interface (IIC) (Optional) Address match: When any slave address matches or the general call address is received in 2 slave receive mode with I C bus format (including address reception after loss of master arbitration) Start condition detection (in master mode) Stop condition detection (in slave mode) • Selection of 16 internal clocks (in master mode) • Direct bus drive (SCL/SDA pin) Four pins—P52/SCL0, P97/SDA0, P86/SCL1, and P42/SDA1 —(normally NMOS pushpull outputs) functi
2 Section 16 I C Bus Interface (IIC) (Optional) 2 Figure 16.1 shows a block diagram of the I C bus interface. Figure 16.2 shows an example of I/O 2 pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 28, Electrical Characteristics.
2 Section 16 I C Bus Interface (IIC) (Optional) VDD VCC VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out SCL in (Slave 1) SCL SDA SDA in SCL SDA SCL out (Slave 2) 2 Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) 16.2 Input/Output Pins 2 Table 16.1 summarizes the input/output pins used by the I C bus interface. Table 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3 Register Descriptions 2 The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer to section 3.2.
2 Section 16 I C Bus Interface (IIC) (Optional) Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR. 2 If I C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the 2 second slave address.
2 Section 16 I C Bus Interface (IIC) (Optional) Table 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.4 2 I C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 MSB-First/LSB-First Select R/W 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit 2 This bit is valid only in master mode with the I C bus format.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected.
2 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.3 I C Transfer Rate STCR ICMR Bits 5 and 6 Bit 5 Bit 4 Bit 3 IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz 0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz 517 kHz* 714 kHz* 0 0 0 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz* 0 0 1 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz* 0 0 1 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 1 0 0 φ/80 62.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.5 2 I C Bus Control Register (ICCR) 2 ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 I C Bus Interface Enable R/W 2 2 2 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 5 MST 0 [MST clearing conditions] 4 TRS 0 R/W 1. When 0 is written by software 2 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 2 BBSY 0 R/W Bus Busy 0 SCP 1 W Start Condition/Stop Condition Prohibit In master mode: • • Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: • Writing to the BBSY flag is disabled.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 1 IRIC 0 Description 2 R/(W)* I C Bus Interface Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 16.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 1 IRIC 0 Description R/(W)* Clocked synchronous serial format and formatless modes: • • • At the end of data transfer (rise of the 8th transmit/receive clock with serial format selected and rise of the 9th transmit/receive clock with formatless selected) When a start condition is detected with serial format selected When the SW bit in DDCSWR is set to 1 When the ICDRE or ICDRF flag is set to 1 in any operating mode: •
2 Section 16 I C Bus Interface (IIC) (Optional) transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Tables 16.4 and 16.5 show the relationship between the flags and the transfer states. Table 16.
2 Section 16 I C Bus Interface (IIC) (Optional) Table 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.6 2 I C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 16.4 and 16.5. Bit Bit Name Initial Value R/W 7 ESTP 0 Description R/(W)* Error Stop Condition Detection Flag 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 5 IRTR 0 Description R/(W)* I C Bus Interface Continuous Transfer Interrupt Request Flag 2 2 Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 3 AL 0 Description R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 1 ADZ 0 Description R/(W)* General Call Address Recognition Flag 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 0 ACKB 0 Acknowledge Bit R/W Stores acknowledge data.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.7 DDC Switch Register (DDCSWR) DDCSWR controls the IIC_0 automatic format switching function and IIC internal latch clearance.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W 3 CLR3 1 2 CLR2 1 W* 2 W* 2 1 CLR1 1 2 W* 0 CLR0 1 W* 2 Description IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.3.8 2 I C Bus Extended Control Register (ICXR) 2 ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description 7 STOPIM 0 Stop Condition Interrupt Source Mask R/W Enables or disables the interrupt generation when the stop condition is detected in slave mode.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 5 ICDRF 0 Receive Data Read Request Flag R Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 4 ICDRE 0 Transmit Data Write Request Flag R Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to.
2 Section 16 I C Bus Interface (IIC) (Optional) Bit Bit Name Initial Value R/W Description 3 ALIE 0 Arbitration Lost Interrupt Enable R/W Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.4 Operation 2 2 The I C bus interface has an I C bus format and a serial format. 16.4.1 2 I C Bus Data Format 2 The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3. The first frame following a start condition always consists of 9 bits. IIC_0 only is capable of formatless operation, as shown in figure 16.4. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.5.
2 Section 16 I C Bus Interface (IIC) (Optional) FS=1 and FSX=1 S DATA DATA P 1 8 n 1 1 m Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) 2 Figure 16.5 I C Bus Data Format (Serial Format) SDA SCL S 1–7 8 9 SLA R/W A 1–7 8 DATA 9 A 1–7 DATA 8 9 A/A P 2 Figure 16.6 I C Bus Timing 2 Table 16.6 I C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.4.2 Initialization Initialize the IIC by the procedure shown in figure 16.7 before starting transmission/reception of data.
2 Section 16 I C Bus Interface (IIC) (Optional) Start Initialize IIC [1] Initialization Read BBSY flag in ICCR [2] Test the status of the SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode. Set BBSY =1 and SCP = 0 in ICCR [4] Start condition issuance Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR [6] Set transmit data for the first byte (slave address + R/W).
2 Section 16 I C Bus Interface (IIC) (Optional) The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR.
2 Section 16 I C Bus Interface (IIC) (Optional) 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
2 Section 16 I C Bus Interface (IIC) (Optional) Start condition issuance SCL (master output) 8 9 SDA Bit 0 (master output) Data 1 SDA (slave output) [7] 1 2 3 4 Bit 7 Bit 6 Bit 5 Bit 4 5 6 7 8 Bit 3 Bit 2 Bit 1 Bit 0 9 [10] Data 2 A A ICDRE IRIC IRTR ICDR Data 1 User processing [9] ICDR write Data 2 [9] IRIC clear [11] ACKB read [12] Set BBSY=1and SCP=0 (Stop condition issuance) [12] IRIC clear Figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) Receive Operation Using the HNDS Function (HNDS = 1): Figure 16.11 shows the sample flowchart for the operations in master receive mode (HNDS = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR [1] Select receive mode. Set HNDS = 1 in ICXR Clear IRIC flag in ICCR Last receive? Yes [2] Start receiving. The first read is a dummy read.
2 Section 16 I C Bus Interface (IIC) (Optional) The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception.
2 Section 16 I C Bus Interface (IIC) (Optional) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 2 Bit 7 Bit 6 9 [3] Data 1 SDA (master output) Data 2 A IRIC IRTR ICDRF ICDRR User processing Data 1 Undefined value [1] TRS = 0 clear [2] ICDR read (Dummy read) [5] ICDR read (Data 1) [4] IRIC clear
2 Section 16 I C Bus Interface (IIC) (Optional) Master receive mode Set TRS = 0 in ICCR [1] Select receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR [2] Start receiving. The first read is a dummy read.
2 Section 16 I C Bus Interface (IIC) (Optional) Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR [1] Select receive mode. Clear IRIC flag in ICCR Set WAIT = 0 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Yes No Set ACKB = 1 in ICSR [7] Set acknowledge data for the last reception.
2 Section 16 I C Bus Interface (IIC) (Optional) The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 16.15. 1.
2 Section 16 I C Bus Interface (IIC) (Optional) 11. Clear the IRIC flag to 0. 12. The IRIC flag is set to 1 in either of the following cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received.
2 Section 16 I C Bus Interface (IIC) (Optional) Master tansmit mode SCL (master output) SDA (slave output) Master receive mode 9 1 2 A Bit 7 Bit 6 3 Bit 5 4 5 6 7 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 9 Bit 7 [3] SDA (master output) 1 2 Bit 6 3 4 5 Bit 5 Bit 4 Bit 3 Data 2 [3] A IRIC [4]IRTR=0 IRTR [4] IRTR=1 ICDR Data 1 User processing [1] TRS cleared to 0 IRIC cleard to 0 [6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1) [2] ICDR r
2 Section 16 I C Bus Interface (IIC) (Optional) 16.4.5 Slave Receive Operation 2 In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. Receive Operation Using the HNDS Function (HNDS = 1): Figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) Slave receive mode [1] Initialization. Select slave receive mode. Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Read IRIC flag in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
2 Section 16 I C Bus Interface (IIC) (Optional) The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2.
2 Section 16 I C Bus Interface (IIC) (Optional) Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) [7] SCL is fixed low until ICDR is read 1 2 3 4 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Slave address Bit 2 Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 [6] A Interrupt request occurrence IRIC ICDRF Address+R/W ICDRS ICDRR User processing Address+R/W Undefined value [2] ICDR re
2 Section 16 I C Bus Interface (IIC) (Optional) [7] SCL is fixed low until ICDR is read SCL (master output) 8 9 1 2 [7] SCL is fixed low until ICDR is read 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Stop condition generation 9 SCL (slave output) SDA (master output) Bit 0 Bit 7 [6] Data (n-1) SDA (slave output) Bit 6 [6] Data (n) A [11] A IRIC ICDRF ICDRS ICDRR User processing Data (n-1) Data (n-2) Data (n) Data (n-1) [8] IRIC clear [5] ICDR read (Data (n-1)) [9]
2 Section 16 I C Bus Interface (IIC) (Optional) Slave receive mode Set MST = 0 and TRS = 0 in ICCR [1] Select slave receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
2 Section 16 I C Bus Interface (IIC) (Optional) The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3.
2 Section 16 I C Bus Interface (IIC) (Optional) Start condition issuance SCL (master output) SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave address 9 1 2 3 4 Bit 7 Bit 6 Bit 5 Bit 4 [6] R/W SDA (slave output) Data 1 A IRIC ICDRF ICDRS Address+R/W Data 1 [7] ICDRR Address+R/W User processing [8] IRIC clear [10] ICDR read Figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 16.24 shows the sample flowchart for the operations in slave transmit mode.
2 Section 16 I C Bus Interface (IIC) (Optional) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2.
2 Section 16 I C Bus Interface (IIC) (Optional) 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 16.26 to 16.28 show the IRIC set timing and SCL control.
2 Section 16 I C Bus Interface (IIC) (Optional) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA 8 9 1 2 3 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL SDA 8 9 1 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL SDA 7 8 7 8 1 2 1 3 2 3 4 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL SDA 7 8 1 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) • Settings of bits other than TRS in ICCR that allow I C bus format operation 2 2 Automatic switching is performed from formatless mode to the I C bus format when the SW bit in DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching 2 from the I C bus format to formatless mode is achieved by setting the SW bit in DDCSWR to 1 by software.
2 Section 16 I C Bus Interface (IIC) (Optional) Table 16.
2 Section 16 I C Bus Interface (IIC) (Optional) Sampling clock C C SCL or SDA input signal D Q Latch D Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 16.29 Block Diagram of Noise Canceler 16.4.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit.
2 Section 16 I C Bus Interface (IIC) (Optional) Notes on Initialization: • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. • When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction.
2 Section 16 I C Bus Interface (IIC) (Optional) 16.5 Interrupt Sources The IIC has interrupt sources IICI and DDCSWI. Table 16.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR and DDCSWR, and are sent to the interrupt controller independently. An IICI interrupt can activate the DTC to allow data transfer. Table 16.8 IIC Interrupt Sources Channel 0 1 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.9 I C Bus Timing (SCL and SDA Outputs) Item Symbol Output Timing Unit Notes SCL output cycle time tSCLO 28tcyc to 256tcyc ns SCL output high pulse width tSCLHO 0.5tSCLO ns See figure 28.29. SCL output low pulse width tSCLLO 0.5tSCLO ns SDA output bus free time tBUFO 0.5tSCLO – 1tcyc ns Start condition output hold time tSTAHO 0.
2 Section 16 I C Bus Interface (IIC) (Optional) Table 16.10 Permissible SCL Rise Time (tsr) Values Time Indication [ns] 2 IICX tcyc Indication 0 7.5 tcyc 1 17.5 tcyc I C Bus Specification φ = (Max.) 5 MHz φ= 1000 1000 937 750 468 375 High-speed mode 300 300 300 300 300 300 Standard mode 100 1000 1000 1000 875 300 300 300 300 300 Standard mode 1000 High-speed mode 300 φ= φ= φ= 8 MHz 10 MHz 16 MHz 20 MHz 2 6.
2 Section 16 I C Bus Interface (IIC) (Optional) 2 Table 16.11 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication tSCLHO 0.5 tSCLO (–tSr) tSCLLO tBUFO tSTAHO tSTASO φ= φ= φ= 10 MHz 16 MHz 20 MHz –1000 4000 4000 4000 4000 4000 4000 High-speed mode –300 600 950 950 950 950 950 Standard mode 4700 4750 High-speed mode –250 1300 1000* Standard mode 4700 High-speed mode –300 0.
2 Section 16 I C Bus Interface (IIC) (Optional) 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
2 Section 16 I C Bus Interface (IIC) (Optional) 8. Notes on start condition issuance for retransmission Figure 16.31 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated. Rev. 3.
2 Section 16 I C Bus Interface (IIC) (Optional) No IRIC = 1? [1] [1] Wait for end of 1-byte transfer Yes [2] Determine whether SCL is low Clear IRIC in ICSR Start condition issuance? No Other processing Yes [3] Issue start condition instruction for retransmission [4] Determine whether start condition is generated or not Read SCL pin No SCL = Low? [5] Set transmit data (slave address + R/W) [2] Yes Set BBSY = 1, SCP = 0 (ICSR) [3] No IRIC = 1? Note:* Program so that processing from [3] to
2 Section 16 I C Bus Interface (IIC) (Optional) 2 9. Note on when I C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
2 Section 16 I C Bus Interface (IIC) (Optional) 10. Notes on WAIT Function Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall.
2 Section 16 I C Bus Interface (IIC) (Optional) 11. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be 2 inserted by driving the SCL pin low is used when the wait function is used in I C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below.
2 Section 16 I C Bus Interface (IIC) (Optional) 12. Note on ICDR read and ICCR access in slave transmit mode 2 In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 16.35. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling.
2 Section 16 I C Bus Interface (IIC) (Optional) 13. Note on TRS bit setting in slave mode 2 In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 16.36), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 16.
2 Section 16 I C Bus Interface (IIC) (Optional) 14. Notes on Arbitration Lost in Master Mode 2 The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address.
2 Section 16 I C Bus Interface (IIC) (Optional) (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. 15.
Section 17 Keyboard Buffer Controller Section 17 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 17.1 shows a block diagram of the keyboard buffer controller. 17.
Section 17 Keyboard Buffer Controller Internal data bus KCLK (PS2AC, PS2BC, PS2CC) KDI Control logic KCLKI KBCRH Parity Bus interface KD (PS2AD, PS2BD, PS2CD) Module data bus KBBR KDO KBCRL KCLKO Register counter value KBI interrupt Legend: KD: KCLK: KBBR: KBCRH: KBCRL: KBC data I/O pin KBC clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L Figure 17.1 Block Diagram of Keyboard Buffer Controller Rev. 3.
Section 17 Keyboard Buffer Controller Figure 17.2 shows how the keyboard buffer controller is connected. Vcc Vcc System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer controller (This LSI) I/F Figure 17.2 Keyboard Buffer Controller Connection 17.2 Input/Output Pins Table 17.1 lists the input/output pins used by the keyboard buffer controller. Table 17.
Section 17 Keyboard Buffer Controller 17.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) • Keyboard data buffer register (KBBR) 17.3.1 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer controller.
Section 17 Keyboard Buffer Controller Bit Bit Name Initial Value R/W Description 3 KBIE 0 R/W Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer controller to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled 2 KBF 0 R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR.
Section 17 Keyboard Buffer Controller 17.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer controller pin output. Bit Bit Name Initial Value R/W Description 7 KBE 0 R/W Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls KBC clock I/O pin output.
Section 17 Keyboard Buffer Controller Bit Bit Name Initial Value R/W Description 3 RXCR3 0 R Receive Counter 2 RXCR2 0 R 1 RXCR1 0 R 0 RXCR0 0 R These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received.
Section 17 Keyboard Buffer Controller 17.4 Operation 17.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4. Start [1] Set the KBIOE bit to 1 in KBCRL.
Section 17 Keyboard Buffer Controller Receive processing/ error handling KCLK (pin state) 1 KD (pin state) Start bit 2 0 3 1 9 7 10 Flag cleared 11 Parity bit Stop bit KCLK (input) KCLK (output) Automatic I/O inhibit KB7 to KB0 Previous data KB0 KB1 Receive data PER KBS KBF [1] [2] [3] [4] [5] [6] Figure 17.4 Receive Timing 17.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side.
Section 17 Keyboard Buffer Controller Start Set KBIOE bit [1] [1] Set the KBE bit to 1 in KBCRH. Read KBCRH [2] [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). KCLKI and KDI bits both 1? Yes Set I/O inhibit (KCLKO = 0) No [3] Write 0 in the KBE bit (prohibit KBBR receive operation). 2 KDO remains at 1 (Continued on [4] Write 0 in the KDO bit (set start bit).
Section 17 Keyboard Buffer Controller 1 Read KBCRH KCLKI = 0? No 2 Yes KDI = 0? * No [7] Keyboard side in data transmission state. Execute receive abort processing. Yes [8] Read KBCRH KCLK = 1? No Error handling Yes Transmit end state (KCLK = high, KD = high) To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 17.5 (2) Sample Transmit Processing Flowchart Rev. 3.
Section 17 Keyboard Buffer Controller KCLK (pin state) 1 KD (pin state) KCLK (output) Start bit 2 8 9 10 11 0 1 7 Parity bit Stop bit 0 1 7 Parity bit Stop bit I/O inhibit KD (output) Start bit KCLK (input) Receive completed notification KD (input) [1] [2] [3] [4] [5] [6] [7] [8] Figure 17.6 Transmit Timing 17.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc.
Section 17 Keyboard Buffer Controller [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation.
Section 17 Keyboard Buffer Controller Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 17.7 (2) Sample Receive Abort Processing Flowchart Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period.
Section 17 Keyboard Buffer Controller 17.4.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. T1 T2 φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.9 KCLKI and KDI Read Timing Rev. 3.
Section 17 Keyboard Buffer Controller 17.4.5 KCLKO and KDO Write Timing Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 T2 φ* Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.10 KCLKO and KDO Write Timing Rev. 3.
Section 17 Keyboard Buffer Controller 17.4.6 KBF Setting Timing and KCLK Control Figure 17.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK (pin) 11th fall Internal KCLK Falling edge signal RXCR3 to RXCR0 B'1010 B'0000 KBF KCLK (output) Automatic I/O inhibit Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 3.
Section 17 Keyboard Buffer Controller 17.4.7 Receive Timing Figure 17.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 N N+1 N+2 Internal KD (KDI) KBBR7 to KBBR0 Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.12 Receive Counter and KBBR Data Load Timing Rev. 3.
Section 17 Keyboard Buffer Controller 17.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.13 shows the setting method and an example of operation.
Section 17 Keyboard Buffer Controller 17.5 Usage Notes 17.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the timing of KBIOE setting and KCLK falling edge detection.
Section 18 Host Interface X-Bus Interface (XBS) Section 18 Host Interface X-Bus Interface (XBS) This LSI has an on-chip host interface (HIF) that enables connection to the ISA bus (X-BUS) and has an on-chip LPC interface. In the following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively. The XBS provides a four-channel parallel interface between the chip’s internal CPU and a host processor.
Section 18 Host Interface X-Bus Interface (XBS) Figure 18.1 shows a block diagram of the XBS.
Section 18 Host Interface X-Bus Interface (XBS) 18.2 Input/Output Pins Table 18.1 lists the input and output pins of the XBS module. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) 18.3 Register Descriptions XBS has the following registers. XBS registers HICR, IDR_1, IDR_2, ODR_1, ODR_2, STR_1, and STR_2 can only be accessed when the HIE bit is set to 1 in SYSCR. For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Section 18 Host Interface X-Bus Interface (XBS) Bit Bit Name Initial Value R/W Description 3 SDE 0 R/W Shutdown Enable 0: Host interface pin shutdown function disabled 1: Host interface pin shutdown function enabled When the shutdown function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin.
Section 18 Host Interface X-Bus Interface (XBS) 18.3.2 Host Interface Control Register (HICR) Host Interface Control Register 2 (HICR2) HICR controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2 controls host interface channel 3 and 4 interrupts. • HICR Bit Bit Name 7 to 3 R/W Initial Value Slave Host Description All 1 Reserved These bits are always read as 1 and cannot be modified.
Section 18 Host Interface X-Bus Interface (XBS) Bit Bit Name Initial Value 0 FGA20E 0 R/W Slave Host Description R/W Fast A20 Gate Function Enable When P81DDR=0: 0: XBS fast A20 gate function disabled 1: Setting prohibited When P81DDR=1: 0: XBS fast A20 gate function disabled 1: XBS fast A20 gate function enabled When the fast A20 gate is disabled, the normal A20 gate can be implemented by the firmware operation of the P81 output.
Section 18 Host Interface X-Bus Interface (XBS) • HICR2 Bit Bit Name 7 to 3 R/W Initial Value Slave Host Description All 1 Reserved These bits are always read as 1, and cannot be modified. 2 IBFIE4 0 R/W Input Data Register Full Interrupt Enable 4 Enables or disables the IBF4 interrupt to the internal CPU.
Section 18 Host Interface X-Bus Interface (XBS) 18.3.3 Input Data Register (IDR) IDR is a register in which data to be input from the host processor to the slave processor (this LSI) is stored. R/W Bit Bit Name Initial Value 7 IDR7 R W 6 IDR6 R W 5 IDR5 R W 4 IDR4 R W 3 IDR3 R W 2 IDR2 R W 1 IDR1 R W 0 IDR0 R W 18.3.
Section 18 Host Interface X-Bus Interface (XBS) 18.3.5 Status Register (STR) STR indicates status information during host interface processing. Bit Bit Name 7 to 4 DBU R/W Initial Value Slave Host Description All 0 R/W R Defined by User The user can use these bits as necessary. 3 C/D 0 R R Command/Data Receives the HA0 input when the host processor writes to IDR, and indicates whether IDR contains data or a command.
Section 18 Host Interface X-Bus Interface (XBS) Table 18.2 shows the conditions for setting and clearing the STR flags. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) Table 18.3 shows HIF host interface channel selection and pin operation. Table 18.3 Host Interface Channel Selection and Pin Operation HI12E CS2E CS3E CS4E Operation 0 — — — Host interface functions halted 1 0 0 0 Host interface channel 1 only operating Operation of channels 2 to 4 halted Pins P43, P81, P90, and PB0 to PB3 operate as I/O ports. CS2 or ECS2, CS3, and CS4 inputs do not operate.
Section 18 Host Interface X-Bus Interface (XBS) 18.4.2 Control States Table 18.4 shows host interface operations from the HIF host, and slave (this LSI) operation. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 18.5 lists the conditions that set and clear GA20 (P81). Figure 18.2 shows the GA20 output in flowchart form. Table 18.6 indicates the GA20 output signal values. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) Table 18.
Section 18 Host Interface X-Bus Interface (XBS) This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the highlevel state, the pins are restored to their normal operation as host interface pins. Table 18.7 shows the scope of HIF pin shutdown. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) 18.5 Interrupt Sources 18.5.1 IBF1, IBF2, IBF3, and IBF4 The host interface can issue four interrupt requests to the slave processor: IBF1 to IBF4. They are input buffer full interrupts for input data registers IDR_1 to IDR_4 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 18.
Section 18 Host Interface X-Bus Interface (XBS) Table 18.
Section 18 Host Interface X-Bus Interface (XBS) HIRQ Setting/Clearing Conflict: If there is conflict between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is executed after completion of the read/write. 18.6 Usage Notes 18.6.
Section 18 Host Interface X-Bus Interface (XBS) Rev. 3.
Section 19 Host Interface LPC Interface (LPC) Section 19 Host Interface LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports only I/O read cycle and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the host interface. 19.
Section 19 Host Interface LPC Interface (LPC) Figure 19.1 shows a block diagram of the LPC.
Section 19 Host Interface LPC Interface (LPC) 19.2 Input/Output Pins Table 19.1 lists the input and output pins of the LPC module. Table 19.
Section 19 Host Interface LPC Interface (LPC) 19.3 Register Descriptions The LPC has the following registers. The settings of XBS related bits do not affect the operation of this LSI’s LPC. However, for reasons relating to the configuration of the program development tool (emulator), when the LPC is used, bit HI12E in SYSCR2 should not be set to 1. For details, see section 3.2.2, System Control Register (SYSCR), and section 18.3.1, System Control Register 2 (SYSCR2).
Section 19 Host Interface LPC Interface (LPC) 19.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 FGA20E 0 R/W — Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output. When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 PMEE 0 R/W — PME output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the PME output function is used, the DDR bit for P80 must not be set to 1.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 LSCIE 0 R/W — LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the LSCI output function is used, the DDR bit for PB1 must not be set to 1. Legend: X: Don't care Rev. 3.
Section 19 Host Interface LPC Interface (LPC) • HICR1 R/W Bit Bit Name Initial Value Slave Host Description 7 LPCBSY 0 R/W — LPC Busy Indicates that the host interface is processing a transfer cycle.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 6 CLKREQ 0 R — LCLK Request Indicates that the host interface’s SERIRQ output is requesting a restart of LCLK.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 LRSTB 0 — — LPC Software Reset Bit Resets the host interface. For the scope of initialization by an LPC reset, see section 19.4.4, Host Interface Shutdown Function (LPCPD).
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 LSMIB 0 R/W — LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0. 0 LSCIB 0 R/W — LSCI output Bit Controls LSCI output in combination with the LSCIE bit. For details, refer to description on the LSCIE bit in HICR0. 19.3.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 5 SDWN 0 R/(W)* — LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 IBFIE2 0 R/W — IDR2 Receive Completion Interrupt Enable Enables or disables IBFI2 interrupt to the slave processor (this LSI).
Section 19 Host Interface LPC Interface (LPC) 19.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Section 19 Host Interface LPC Interface (LPC) Table 19.
Section 19 Host Interface LPC Interface (LPC) 19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit read-only registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 selection, see section 19.3.3, LPC Channel 3 Address Register (LADR3).
Section 19 Host Interface LPC Interface (LPC) I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 1 0 0 I/O read STR1 read 0000 0000 0110 0 1 1 0 I/O read STR2 read • STR1 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU17 0 R/W R Defined by User 6 DBU16 0 R/W R The user can use these bits as necessary.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 OBF1 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. Cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 IBF2 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3.
Section 19 Host Interface LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave Host Description 7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor (this LSI). IBF3B is cleared to 0 when the slave processor reads TWR15.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 SWMF 0 R/(W)* R Slave Write Mode Flag Set to 1 when the slave processor (this LSI) writes to TWR0. In the event of simultaneous writes by the master and the slave, the master write has priority.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 OBF3A 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. OBF3A is cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 IBF3A 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.3.
Section 19 Host Interface LPC Interface (LPC) • SIRQCR0 R/W Bit Bit Name Initial Value Slave Host Description 7 Q/C 0 R — Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] • LPC hardware reset, LPC software reset • Specification by SERIRQ transfer cycle stop frame 1: Quiet mode [Setting condition] Specification by SERIRQ transfer cycle stop frame.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W — Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 SMIE2 0 R/W — Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ1E1 0 R/W — Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request when OBF1 is set by an ODR1 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 6 IRQ10E3 0 R/W — Host IRQ10 Interrupt Enable 3 Enables or disables a host IRQ10 interrupt request when OBF3A is set by an ODR3 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 IRQ6E3 0 R/W — Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request when OBF3A is set by an ODR3 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 IRQ10E2 0 R/W — Host IRQ10 Interrupt Enable 2 Enables or disables a host IRQ10 interrupt request when OBF2 is set by an ODR2 write.
Section 19 Host Interface LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ6E2 0 R/W — Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request when OBF2 is set by an ODR2 write.
Section 19 Host Interface LPC Interface (LPC) 19.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt request signal of each frame. R/W Bit Bit Name Initial Value Slave Host Description 7 SELSTR3 0 W STR3 Register Function Select 3 Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. See description on STR3 in section 19.3.7, Status Registers 1 to 3 (STR1 to STR3), for details.
Section 19 Host Interface LPC Interface (LPC) 19.4 Operation 19.4.1 Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in singlechip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins.
Section 19 Host Interface LPC Interface (LPC) If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the host interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed.
Section 19 Host Interface LPC Interface (LPC) LCLK LFRAME LAD3–LAD0 Start ADDR TAR Sync Data TAR Start Cycle type, direction, and size Number of clocks 1 1 4 2 1 2 2 1 Figure 19.2 Typical LFRAME Timing LCLK LFRAME LAD3–LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Too many Syncs cause timeout Figure 19.3 Abort Mechanism Rev. 3.
Section 19 Host Interface LPC Interface (LPC) 19.4.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data.
Section 19 Host Interface LPC Interface (LPC) Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 19.4 GA20 Output Rev. 3.
Section 19 Host Interface LPC Interface (LPC) Table 19.
Section 19 Host Interface LPC Interface (LPC) 19.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit.
Section 19 Host Interface LPC Interface (LPC) Table 19.5 shows the scope of the host interface pin shutdown. Table 19.
Section 19 Host Interface LPC Interface (LPC) The scope of the initialization in each mode is shown in table 19.6. Table 19.
Section 19 Host Interface LPC Interface (LPC) Figure 19.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3–LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 19.5 Power-Down State Termination Timing Rev. 3.
Section 19 Host Interface LPC Interface (LPC) 19.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 19.6.
Section 19 Host Interface LPC Interface (LPC) Serial Interrupt Transfer Cycle Drive Source Number of States Start Slave Host 6 1 IRQ0 Slave 3 2 IRQ1 Slave 3 Drive possible in LPC channel 1 3 SMI Slave 3 Drive possible in LPC channels 2 and 3 4 IRQ3 Slave 3 5 IRQ4 Slave 3 6 IRQ5 Slave 3 7 IRQ6 Slave 3 8 IRQ7 Slave 3 9 IRQ8 Slave 3 10 IRQ9 Slave 3 Drive possible in LPC channels 2 and 3 11 IRQ10 Slave 3 Drive possible in LPC channels 2 and 3 12 IRQ11 Slave
Section 19 Host Interface LPC Interface (LPC) clock must first be issued to the host. For details see section 19.4.6, Host Interface Clock Start Request (CLKRUN). 19.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host.
Section 19 Host Interface LPC Interface (LPC) 19.5 Interrupt Sources 19.5.1 IBFI1 to IBFI3, and ERRI The host interface has four interrupt requests for the slave processor (this LSI): IBF1 to IBF3, and ERRI. IBFI1 to IBFI3 are IDR receive complete interrupts for IDR1 to IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding enable bit. Table 19.
Section 19 Host Interface LPC Interface (LPC) Table 19.8 summarizes the methods of setting and clearing these bits, and figure 19.8 shows the processing flowchart. Table 19.
Section 19 Host Interface LPC Interface (LPC) Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 No SERIRQ IRQ1 output Interrupt initiation SERIRQ IRQ1 source clearance ODR1 read OBF1 = 0? Yes No All bytes transferred? Hardware operation Yes Software operation Figure 19.8 HIRQ Flowchart (Example of Channel 1) 19.6 Usage Notes 19.6.1 Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop control register. The initial setting is for LPC operation to be halted.
Section 19 Host Interface LPC Interface (LPC) Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 19.9 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15 when LADR3 = H'A24F and LADR3 = H'3FD0. Table 19.
Section 20 D/A Converter Section 20 D/A Converter 20.1 Features • 8-bit resolution • Two output channels • Conversion time: Max. 10 µs (when load capacitance is 20 pF) • Output voltage: 0 V to AVref • D/A output retaining function in software standby mode Internal data bus Bus interface Module data bus AVref AVCC DA1 8-bit D/A D A D R 0 D A D R 1 D A C R DA0 AVSS Control circuit Legend: DACR : D/A control register DADR0 : D/A data register 0 DADR1 : D/A data register 1 Figure 20.
Section 20 D/A Converter 20.2 Input/Output Pins Table 20.1 summarizes the input/output pins used by the D/A converter. Table 20.
Section 20 D/A Converter 20.3.2 D/A Control Register (DACR) DACR controls D/A converter operation. Bit Bit Name Initial Value R/W Description 7 DAOE1 0 R/W D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output.
Section 20 D/A Converter Table 20.2 D/A Channel Enable Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE Description 0 0 — Disables D/A conversion 1 0 Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 1 0 1 Enables D/A conversion for channels 0 and 1 0 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 1 20.
Section 20 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle φ Address Conversion data (1) DADR0 Conversion data (2) DAOE0 Conversion result (2) Conversion result (1) DA0 High impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 20.2 D/A Converter Operation Example 20.
Section 20 D/A Converter Rev. 3.
Section 21 A/D Converter Section 21 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels and up to 16 digital input to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 21.
Section 21 A/D Converter A block diagram of the A/D converter is shown in figure 21.1.
Section 21 A/D Converter 21.2 Input/Output Pins Table 21.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. Expanded A/D conversion input pins (CIN0 to CIN15) can be selected with the AN6 and AN7 pins. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 21.
Section 21 A/D Converter 21.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) • A/D control register (ADCR) • Keyboard comparator control register (KBCOMP) 21.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
Section 21 A/D Converter 21.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Section 21 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W 0 CH0 0 R/W Select analog input channels. The input channel setting must be made when conversion is halted (ADST = 0).
Section 21 A/D Converter 21.3.4 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the CIN input channel for which A/D conversion is performed and enables or disables the comparator scan function of CIN7 to CIN0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W 6 IrCKS2 0 R/W These bits are related to the SCI. For details, refer to section 15.3.10, Keyboard Comparator Control Register (KBCOMP).
Section 21 A/D Converter 21.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 21.4.
Section 21 A/D Converter Figure 21.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4.
Section 21 A/D Converter 21.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 21.3 shows the A/D conversion timing. Table 21.3 indicates the A/D conversion time. As indicated in figure 21.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Section 21 A/D Converter Table 21.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol min typ max min typ max A/D conversion start delay time tD 10 — 17 6 — 9 Input sampling time tSPL — 63 — — 31 — A/D conversion time tCONV 259 — 266 131 — 134 Note: 21.4.4 * Values in the table indicate the number of states. External Trigger Input Timing A/D conversion can be externally triggered.
Section 21 A/D Converter 21.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. 21.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below.
Section 21 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 21.5 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 21.6 A/D Conversion Accuracy Definitions Rev. 3.
Section 21 A/D Converter 21.7 Usage Notes 21.7.1 Permissible Signal Source Impedance This LSI’s analog input (3-V version) is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 21 A/D Converter 21.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ ANn ≤ AVref (n = 0 to 7). • Digital input voltage range The voltage applied to digital input pin CINn should be in the range AVss ≤ CINn ≤ AVref and Vss ≤ CINn ≤ Vcc (n = 0 to 15).
Section 21 A/D Converter AVCC AVref *1 Rin*2 *1 100 Ω AN0 to AN7 0.1 µF AVSS Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 21.8 Example of Analog Input Protection Circuit 10 kΩ To A/D converter AN0 to AN7 20 pF Note: Values are reference values. Figure 21.9 Equivalent Circuit of Analog Input Pin 21.7.6 Module Stop Mode Setting A/D converter operation can be enabled or disabled using the module stop control register.
Section 22 RAM Section 22 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Section 22 RAM Rev. 3.
Section 23 ROM Section 23 ROM This LSI has an on-chip flash memory. The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 23.1. 23.
Section 23 ROM • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • Two flash memory on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In user program mode, individual blocks can be erased or programmed.
Section 23 ROM 23.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 23.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 23.1. Figure 23.3 shows the boot mode and figure 23.4 shows the user program mode.
Section 23 ROM 1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked.
Section 23 ROM 1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM.
Section 23 ROM 23.3 Block Configuration 23.3.1 Block Configuration of 64-Kbyte Flash Memory Figure 23.5 shows the block configuration of 64-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units.
Section 23 ROM 23.3.2 Block Configuration of 128-Kbyte Flash Memory Figure 23.6 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 32 kbytes (2 blocks), 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units.
Section 23 ROM 23.3.3 Block Configuration of 256-Kbyte Flash Memory Figure 23.7 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80.
Section 23 ROM 23.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 23.2. Table 23.2 Pin Configuration Pin Name I/O Function RES Input Reset MD1 Input Sets this LSI’s operating mode MD0 Input Sets this LSI’s operating mode P92 Input Sets this LSI’s operating mode P91 Input Sets this LSI’s operating mode P90 Input Sets this LSI’s operating mode TxD1 Output Serial transmit data output RxD1 Input Serial receive data input 23.
Section 23 ROM Bit Bit Name Initial Value R/W Description 7 FWE 1 R Flash Write Enable Controls programming/erasing of on-chip flash memory. This bit is always read as 0, and cannot be modified. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, the EV, PV, E, and P bits in this register, the ESU and PSU bits in FLMCR2, and all EBR1 and EBR2 bits cannot be set to 1.
Section 23 ROM 23.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
Section 23 ROM 23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0.
Section 23 ROM • EBR1 (128-kbyte version) Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R/(W) Reserved 1 EB9 0 R/W* When this bit is set to 1, 32 kbytes of EB9 (H'018000 to H'01FFFF) are to be erased. 0 EB8 0 R/W* When this bit is set to 1, 32 kbytes of EB8 (H'010000 to H'017FFF) are to be erased. The initial values should not be modified.
Section 23 ROM • EBR1 (256-kbyte version) Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R/(W) Reserved 3 EB11 0 R/W* When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) are to be erased. 2 EB10 0 R/W* When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) are to be erased. 1 EB9 0 R/W* When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) are to be erased.
Section 23 ROM 23.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. On-chip ROM is enabled or disabled by the mode select pins (MD1 and MD0) and the EXPE bit in MDCR, as summarized in table 23.3.
Section 23 ROM Table 23.4 On-Board Programming Mode Settings Mode Setting MD1 MD0 P92 P91 P90 Boot mode 0 0 1* 1* 1* Mode 2 (advanced mode) 1 0 Mode 3 (normal mode) 1 1 User program mode Note: 23.7.1 * Can be used as an I/O port after the boot mode activation. Boot Mode Table 23.5 shows the boot mode operations between reset end and branching to the programming control program. 1.
Section 23 ROM switches to the programming control program. Figure 23.8 shows the on-chip RAM area in boot mode. 3 6. Before branching to the programming control program (H'FFE088* in the RAM area), this LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD1 pin is in high-level output state.
Section 23 ROM Host Operation Communications Contents Processing Contents Bit rate adjustment Boot mode start Item Table 23.5 Boot Mode Operation Branches to boot program at reset-start. Boot program start Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 H'00 Transmits data H'55 when data H'00 is received error-free.
Section 23 ROM Table 23.
Section 23 ROM H'FFE080 40 FE 64 66 32 31 34 39 ← (Product ID) H8S/2140B, H8S/2141B, H8S/2148B, H8S/2160B, or H8S/2161B Instruction codes of the programming control program H'FFE088 H'FFD080 40 FE 64 66 32 31 34 35 ← (Product ID) H8S/2145B H'FFD088 Instruction codes of the programming control program Figure 23.9 ID Code Area 23.7.
Section 23 ROM Reset-start No Program/erase? Yes Transfer user program/ erase control program to RAM Branch to flash memory application program Branch to user program/ erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode 23.
Section 23 ROM 23.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 23.11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address.
Section 23 ROM Write pulse application subroutine Start of programming Sub-Routine Write Pulse START Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 23 ROM 23.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 23.12 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 23 ROM START *1 Set SWE bit in FLMCR1 Wait (x) µs *2 n=1 Set EBR1 and EBR2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *2 Start of erasing Set E bit in FLMCR1 *2 Wait (z) ms End of erasing Clear E bit in FLMCR1 Wait (α) µs *2 Clear ESU bit in FLMCR2 Wait (β) µs *2 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *2 n←n+1 Set block start address as verify address H'FF dummy write to verify address Wait (ε) µs *2 Read verify data *3 Increment address Verify data = all "1"
Section 23 ROM 23.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 23.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode.
Section 23 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode. 23.
Section 23 ROM 23.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 64/128/256-kbyte flash memory on-chip MCU device*. Figure 23.13 shows a memory map in programmer mode. Note: * For 3-V and 5-V version products, set the programming voltage of the PROM programmer to 3.3V.
Section 23 ROM 23.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. For 3-V and 5-V version products, use a PROM programmer that supports the Renesas 64/128/256-kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. 2.
Section 23 ROM Rev. 3.
Section 24 Clock Pulse Generator Section 24 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 24.1 shows a block diagram of the clock pulse generator.
Section 24 Clock Pulse Generator 24.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 24.1.1 Connecting Crystal Resonator Figure 24.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 24.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 24.3 shows the equivalent circuit of a crystal resonator.
Section 24 Clock Pulse Generator Table 24.2 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 12 16 20 RS (max) (Ω) 500 120 80 70 60 50 40 C0 (max) (pF) 7 7 7 7 7 7 7 24.1.2 External Clock Input Method Figure 24.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less.
Section 24 Clock Pulse Generator Table 24.3 External Clock Input Conditions VCC = 2.7 to 3.6 V VCC = 5.0 V ± 10 % Item Symbol Min Max Min Max Unit Test Conditions External clock input pulse width low level tEXL 40 — 20 — ns Figure 24.5 External clock input pulse width high level tEXH 40 — 20 — ns External clock rising time tEXr — 10 — 5 ns External clock falling time tEXf — 10 — 5 ns Clock pulse width low level tCL 0.4 0.6 0.4 0.
Section 24 Clock Pulse Generator Table 24.4 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item Symbol Min. Max. Unit Remarks External clock output stabilization delay time tDEXT* 500 — µs Figure 24.6 Note: tDEXT includes a RES pulse width (tRESW). * VCC STBY 2.7 V VIH EXTAL φ (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW).
Section 24 Clock Pulse Generator 24.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in SBYCR. 24.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. Inputting the Subclock: To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin.
Section 24 Clock Pulse Generator When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed. Note on Subclock Usage: In transiting to power-down mode, if at least two cycles of the 32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the SLEEP instruction is executed (power-down mode transition), the subclock input circuit is not initialized and an error may occur in the microcomputer.
Section 24 Clock Pulse Generator 24.8 Processing for X1 and X2 Pins The X1 and X2 pins should be open as shown in figure 24.8. X1 Open X2 Open Figure 24.8 Processing for X1 and X2 Pins 24.9 Usage Notes 24.9.1 Note on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user.
Section 25 Power-Down Modes Section 25 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power dissipation is significantly reduced. In addition, there is also module stop mode in which reduced power dissipation can be achieved by individually stopping on-chip peripheral modules.
Section 25 Power-Down Modes 25.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7 SSBY Software Standby 0 R/W Specifies the operating mode to be entered after executing the SLEEP instruction.
Section 25 Power-Down Modes Bit Bit Name Initial Value R/W Description 2 SCK2 0 R/W System Clock Select 2 to 0 1 SCK1 0 R/W 0 SCK0 0 R/W Selects a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, SCK2 to SCK0 must be cleared to B'000.
Section 25 Power-Down Modes 25.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7 DTON Direct Transfer On Flag 0 R/W Specifies the operating mode to be entered after executing the SLEEP instruction.
Section 25 Power-Down Modes Bit Bit Name Initial Value R/W Description 5 NESEL Noise Elimination Sampling Frequency Select 0 R/W Selects the frequency by which the subclock (φSUB) input from the EXCL pin is sampled using the clock (φ) generated by the system clock pulse generator. Clear this bit to 0 when φ is 5 MHz or more. 0: Sampling using φ/32 clock 1: Sampling using φ/4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables/disables subclock input from the EXCL pin.
Section 25 Power-Down Modes • MSTPCRL Bit Bit Name Initial Value R/W Corresponding Module 7 MSTP7 1 R/W Serial communication interface_0 (SCI_0) 6 MSTP6 1 R/W Serial communication interface_1 (SCI_1) 5 MSTP5 1 R/W Serial communication interface_2 (SCI_2) 4 MSTP4 1 R/W I C bus interface_0 (IIC_0) 3 MSTP3 1 R/W I C bus interface_1 (IIC_1) 2 MSTP2 1 R/W Host interface (XBS), keyboard buffer controller, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt
Section 25 Power-Down Modes Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state Hardware standby mode RES pin = High SSBY = 0, LSON = 0 SLEEP instruction High-speed mode (main clock) Sleep mode (main clock) Any interrupt SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 Medium-speed mode (main clock) SLEEP instruction External interrupt*3 SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception handling SLEEP instruction Interrupt
Section 25 Power-Down Modes Table 25.
Section 25 Power-Down Modes 25.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32). On-chip peripheral modules other than the bus masters always operate on the system clock (φ).
Section 25 Power-Down Modes Medium-speed mode φ, peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 25.2 Medium-Speed Mode Timing 25.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU’s internal registers are retained.
Section 25 Power-Down Modes 25.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT_1) is cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop.
Section 25 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 25.3 Application Example in Software Standby Mode 25.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state.
Section 25 Power-Down Modes Figure 25.4 shows an example of hardware standby mode timing. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 25.4 Hardware Standby Mode Timing 25.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Section 25 Power-Down Modes When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. 25.
Section 25 Power-Down Modes 25.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode.
Section 25 Power-Down Modes 25.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle.
Section 25 Power-Down Modes 25.12 Usage Notes 25.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 25.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. 25.12.
Section 25 Power-Down Modes Rev. 3.
Section 26 List of Registers Section 26 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) • Registers are listed from the lower allocation addresses. • The MSB-side address is indicated for 16-bit addresses. • Registers are classified by functional modules. • The access size is indicated. 2.
Section 26 List of Registers 26.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width LPC channel address register H LADR3H 8 H'FE34 LPC 8 3 LPC channel address register L LADR3L 8 H'FE35 LPC 8 3 SERIRQ control register 0 SIRQCR0 8 H'FE36 LPC 8 3 SERIRQ control register 1 SIRQCR1 8 H'FE37 LPC 8 3 Input data register 1 IDR1 8 H'FE38 LPC 8 3 Output data register 1 ODR1 8 H'FE39 LPC 8 3 Status register 1 STR1 8 H'FE3A LP
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Port F data direction register PFDDR* 8 H'FE4B (write) PORT 8 3 Port C output data register PCODR*1 8 H'FE4C PORT 8 3 Port D output data register PDODR*1 8 H'FE4D PORT 8 3 Port C input data register PCPIN*1 8 H'FE4E (read) PORT 8 3 Port C data direction register PCDDR*1 8 H'FE4E (write) PORT 8 3 Port D input data register PDPIN*1 8 H'FE4F (r
Section 26 List of Registers Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Address Keyboard control register L_1 KBCRL_1 8 H'FEDD Keyboard buffer controller_1 8 2 Keyboard data buffer register_1 KBBR_1 8 H'FEDE Keyboard buffer controller_1 8 2 Keyboard control register H_2 KBCRH_2 8 H'FEE0 Keyboard buffer controller_2 8 2 Keyboard control register L_2 KBCRL_2 8 H'FEE1 Keyboard buffer controller_2 8 2 Keyboard data buffer register_2 KBBR_2
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Break address register A BARA 8 H'FEF5 INT 8 2 Break address register B BARB 8 H'FEF6 INT 8 2 Break address register C BARC 8 H'FEF7 INT 8 2 Flash memory control register 1 FLMCR1 8 H'FF80 FLASH 8 2 Flash memory control register 2 FLMCR2 8 H'FF81 FLASH 8 2 Peripheral clock select register PCSR 8 H'FF82 PWM 8 2 Erase block register 1 EBR
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Free running counter L FRCL 8 H'FF93 FRT 8 2 Output control register AH OCRAH 8 H'FF94 FRT 8 2 Output control register BH OCRBH 8 H'FF94 FRT 8 2 Output control register AL OCRAL 8 H'FF95 FRT 8 2 Output control register BL OCRBL 8 H'FF95 FRT 8 2 Timer control register TCR 8 H'FF96 FRT 8 2 Timer output compare control register TOCR 8 H'
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Serial status register_2 SSR_2 8 H'FFA4 SCI_2 8 2 Receive data register_2 RDR_2 8 H'FFA5 SCI_2 8 2 Smart card mode register_2 SCMR_2 8 H'FFA6 SCI_2 8 2 PWM (D/A) counter H DACNTH 8 H'FFA6 PWMX 8 2 PWM (D/A) data register BH DADRBH 8 H'FFA6 PWMX 8 2 PWM (D/A) counter L DACNTL 8 H'FFA7 PWMX 8 2 PWM (D/A) data register BL DADRBL 8 H'FFA7
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Port 6 data register P6DR 8 H'FFBB PORT 8 2 Port B output data register PBODR 8 H'FFBC PORT 8 2 Port B input data register PBPIN 8 H'FFBD (read) PORT 8 2 Port 8 data direction register P8DDR 8 H'FFBD (write) PORT 8 2 Port 7 input data register P7PIN 8 H'FFBE (read) PORT 8 2 Port B data direction register PBDDR 8 H'FFBE (write) PORT 8 2 P
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width PWM output enable register A PWOERA 8 H'FFD3 PWM 8 2 PWM data polarity register B PWDPRB 8 H'FFD4 PWM 8 2 PWM data polarity register A PWDPRA 8 H'FFD5 PWM 8 2 PWM register select PWSL 8 H'FFD6 PWM 8 2 PWM data registers 0 to 15 PWDR0 to PWDR15 8 H'FFD7 PWM 8 2 Serial mode register_0 SMR_0 8 H'FFD8 SCI_0 8 2 I C bus control register_0 IC
Section 26 List of Registers Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Timer control/status register_1 TCSR_1 8 H'FFEA WDT_1 8 2 Timer counter_1 TCNT_1 8 H'FFEA (write) WDT_1 8 2 Timer counter_1 TCNT_1 8 H'FFEB (read) WDT_1 8 2 Host interface control register HICR 8 H'FFF0 XBS 8 2 Timer control register_X TCR_X 8 H'FFF0 TMR_X 16 2 Timer control register_Y TCR_Y 8 H'FFF0 TMR_Y 16 2 Keyboard matrix interrupt
Section 26 List of Registers Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Address Timer connection register I TCONRI 8 H'FFFC Timer connection 8 2 Output data register_2 ODR_2 8 H'FFFD XBS 8 2 Timer connection register O TCONRO 8 H'FFFD Timer connection 8 2 Status register_2 STR_2 8 H'FFFE XBS 8 2 Timer connection register S TCONRS 8 H'FFFE Timer connection 8 2 Edge sense register SEDGR 8 H'FFFF Timer connection 8 2 Module
Section 26 List of Registers 26.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. 16-bit registers are shown as 2 lines.
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SIRQCR0 Q/C SELREQ IEDIR SMIE3B SMIE3A SMIE2 IRQ12E1 IRQ1E1 LPC SIRQCR1 IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2 IDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STR1 DBU17 DBU16 DBU15 DBU14 C/D1 DBU12 IBF1 OBF1 IDR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IDR_4 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 XBS ODR_4 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 STR_4 DBU DBU DBU DBU C/D DBU IBF OBF ICXR_0 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 ICXR_1 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_1 KBCRH_0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS KBCRL_0 KBE KCLKO KDO — RXCR3 RXCR2 RXCR1
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BARC A7 A6 A5 A4 A3 A2 A1 — INT FLMCR1 FWE SWE — — EV PV E P FLASH FLMCR2 FLER — — — — — ESU PSU PCSR — — — — — PWCKB PWCKA — PWM 4 EBR1* — — — — EB11 EB10 EB9 EB8 FLASH SYSCR2 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E SYSTEM EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FLASH SBYCR SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 SYSTEM
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TOCR ICRDMS OCRAMS ICRS OCRS OEA OEB OLVLA OLVLB FRT ICRAH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCRARH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ICRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OCRARL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRBH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PORT P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P2DDR P27DDR P26DDR P25DDR P24D
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCSR_1 CMFB CMFA OVF — OS3 OS2 OS1 OS0 TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_0, TMR_1 TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNT_1 Bi
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRDL AD1 AD0 — — — — — — ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 A/D converter ADCR TRGS1 TRGS0 — — — — — — TCSR_1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 TCNT_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HICR — — — — — IBFIE2 IBFIE1 FGA20E XBS TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_X WDT_1 TCR_Y CMIEB
Section 26 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCONRO HOE VOE CLOE CBOE HOINV VOINV CLOINV CBOINV Timer connection STR_2 DBU27 DBU26 DBU25 DBU24 C/D2 DBU22 IBF2 OBF2 XBS TCONRS TMRX/Y ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 VEDG HEDG CEDG HFEDG VFEDG PREQF IHI IVI Timer connection SEDGR Notes: 1. 2. 3. 4. Can be used on the H8S/2160B and H8S/2161B.
Section 26 List of Registers 26.
Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation Reset STR1 Initialized — — — — — — — Initialized LPC IDR2 — — — — — — — — — ODR2 — — — — — — — — — STR2 Initialized — — — — — — — Initialized HISEL Initialized — — — — — — — Initialized HICR0 Initialized — — — — — — — Initialized HICR1 Initialized — — — — — — — Initialized HICR2 Initialized — — — — — — — Initialized HICR3 — — — — — — — — — WUEMRB*2
Section 26 List of Registers Register Abbreviation Reset ICXR_0 ICXR_1 HighSpeed/ MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module Initialized — — — — — — — Initialized IIC_0 Initialized — — — — — — — Initialized IIC_1 KBCRH_0 Initialized — Initialized — KBCRL_0 Initialized — Initialized — KBBR_0 Initialized — Initialized — KBCRH_1 Initialized — Initialized — KBCRL_1 Initialized — Initialized — Initialized Initialized I
Section 26 List of Registers Register Abbreviation Reset HighSpeed/ MediumSpeed Watch Sleep — PCSR Initialized — — EBR1 Initialized — Initialized — — SubActive SubSleep Module Stop Software Hardware Standby Standby Module — — — — Initialized Initialized — SYSCR2 Initialized — — EBR2 Initialized — Initialized — Initialized Initialized — Initialized Initialized FLASH SBYCR Initialized — — — — — — — Initialized SYSTEM LPWRCR Initialized — — — — — — — Initialized M
Section 26 List of Registers Register Abbreviation Reset HighSpeed/ MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module ICRAL Initialized — — — — — — — Initialized FRT OCRARL Initialized — — — — — — — Initialized ICRBH Initialized — — — — — — — Initialized OCRAFH Initialized — — — — — — — Initialized ICRBL Initialized — — — — — — — Initialized OCRAFL Initialized — — — — — — — Initialized ICRCH Initia
Section 26 List of Registers Register Abbreviation Reset HighSpeed/ MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module P3PCR Initialized — — — — — — — Initialized PORT P1DDR Initialized — — — — — — — Initialized P2DDR Initialized — — — — — — — Initialized P1DR Initialized — — — — — — — Initialized P2DR Initialized — — — — — — — Initialized P3DDR Initialized — — — — — — — Initialized P4DDR Initialize
Section 26 List of Registers Register Abbreviation Reset TCORB_0 TCORB_1 HighSpeed/ MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module Initialized — — — — — — — Initialized — — — — — — — Initialized TMR_0, TMR_1 Initialized TCNT_0 Initialized — — — — — — — Initialized TCNT_1 Initialized — — — — — — — Initialized PWOERB Initialized — — — — — — — Initialized PWM PWOERA Initialized — — — — — — — Initialize
Section 26 List of Registers HighSpeed/ MediumSpeed Register Abbreviation Reset ADCR Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized A/D converter TCSR_1 Initialized — — — — — — — Initialized WDT_1 TCNT_1 Initialized — — — — — — — Initialized HICR Initialized — — — — — — — Initialized XBS TCR_X Initialized — — — — — — — Initialized TMR_X TCR_Y Initialized — — — — — — — Initialized TMR_Y Watch Sleep SubActive SubSl
Section 26 List of Registers Register Abbreviation Reset TCONRO HighSpeed/ MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module Initialized — — — — — — — Initialized Timer connection STR_2 Initialized — — — — — — — Initialized XBS TCONRS Initialized — — — — — — — SEDGR Initialized — — — — — — — Notes: 1. Can be used on the H8S/2160B and H8S/2161B. 2. Not supported by the H8S/2148B and H8S/2145B (5-V version). Rev. 3.
Section 26 List of Registers 26.
Section 26 List of Registers Lower Address Register Name H'FE30 IDR3 H'FE31 ODR3 H'FE32 STR3 H'FE34 LADR3H H'FE35 LADR3L H'FE36 SIRQCR0 H'FE37 SIRQCR1 H'FE38 IDR1 H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition MSTP = 0, (HI12E = 0)* MSTP = 0, (HI12E = 0)* LPC Module Name H'FE39 ODR1 H'FE3A STR1 H'FE3C IDR2 H'FE3D ODR2 H'FE3E STR2 H'FE3F HISEL H'FE40 HICR0 H'FE41 HICR1 H'FE42 HICR2 H'FE43 HICR3 H'
Section 26 List of Registers Lower Address H'FE4E Register Name PCPIN (read) H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition — No condition PORT MSTP2 = 0 MSTP2 = 0 XBS No condition No condition IIC_0 Module Name PCDDR (write) H'FE4F PDPIN (read) PDDDR (write) H'FE80 HICR2 H'FE81 IDR_3 H'FE82 ODR_3 H'FE83 STR_3 H'FE84 IDR_4 H'FE85 ODR_4 H'FE86 STR_4 H'FED4 ICXR_0 H'FED5 ICXR_1 H'FED8 KBCRH_0 H'FED9 KBCRL
Section 26 List of Registers Lower Address Register Name H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition No condition No condition DTC No condition No condition INT FLSHE = 1 in STCR FLSHE = 1 in STCR FLASH Module Name H'FEEE DTCERA H'FEEF DTCERB H'FEF0 DTCERC H'FEF1 DTCERD H'FEF2 DTCERE H'FEF3 DTVECR H'FEF4 ABRKCR H'FEF5 BARA H'FEF6 BARB H'FEF7 BARC H'FF80 FLMCR1 H'FF81 FLMCR2 H'FF82 PCSR FLSHE = 0 i
Section 26 List of Registers Lower Address Register Name H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition MSTP6 = 0 MSTP6 = 0 SCI_1 H'FF8A SCR_1 H'FF8B TDR_1 H'FF8C SSR_1 H'FF8D RDR_1 H'FF8E SCMR_1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR ICDR_1 MSTP3 = 0, IICE = 1 in STCR MSTP3 = 0, IICE = 1 in STCR SARX_1 H'FF8F ICE = 0 in ICCR1 ICE = 1 in ICCR1 ICE = 1 in ICCR1 ICE = 1 in ICCR1 SAR_1 ICE = 0 in I
Section 26 List of Registers Lower Address H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D Register Name ICRAL H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition MSTP13 = 0 ICRS = 0 in TOCR H8S/2160B, H8S/2161B Register Select Condition MSTP13 = 0 ICRS = 0 in TOCR OCRARL ICRS = 1 in TOCR ICRS = 1 in TOCR ICRBH ICRS = 0 in TOCR ICRS = 0 in TOCR OCRAFH ICRS = 1 in TOCR ICRS = 1 in TOCR ICRBL ICRS = 0 in TOCR ICRS = 0 in TOCR OCRAFL ICRS = 1 in TOCR ICRS = 1 in TOCR ICRCH ICRS =
Section 26 List of Registers Lower Address Register Name H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition MSTP5 = 0 MSTP5 = 0 SCI_2 Module Name H'FFA2 SCR_2 H'FFA3 TDR_2 H'FFA4 SSR_2 H'FFA5 RDR_2 H'FFA6 SCMR_2 MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR SCI_2 DADRBH MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB MSTP11 = 0, REGS = 0 in IICE = 1 in DACNT/ STCR DADRB PWMX DACNTH REGS = 1 in DACNT/ D
Section 26 List of Registers Lower Address Register Name H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR H'FFBD P8DDR (write) H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition No condition No condition PORT Module Name PBPIN (read) H'FFBE P7PIN (read) PBDDR (write) H'FFBF P8DR H'FFC0 P9DDR H'FFC1 P9DR H'FFC2 IER No condition No condition INT H'FFC3 STCR No condition
Section 26 List of Registers Lower Address Register Name H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition No condition No condition PWM MSTP11 = 0 MSTP11 = 0 PWM Module Name H'FFD2 PWOERB H'FFD3 PWOERA H'FFD4 PWDPRB H'FFD5 PWDPRA H'FFD6 PWSL H'FFD7 PWDR0 to PWDR15 H'FFD8 SMR_0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR SCI_0 ICCR_0 MSTP4 = 0, IICE = 1 in STCR MSTP4 = 0, IICE = 1 in STCR IIC_0 BRR_
Section 26 List of Registers Lower Address Register Name H'FFE0 ADDRAH H'FFE1 ADDRAL H'FFE2 ADDRBH H'FFE3 ADDRBL H'FFE4 ADDRCH H'FFE5 ADDRCL H'FFE6 ADDRDH H'FFE7 ADDRDL H'FFE8 ADCSR H'FFE9 ADCR H'FFEA TCSR_1 H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition MSTP9 = 0 MSTP9 = 0 A/D No condition No condition WDT_1 Module Name TCNT_1 (write) H'FFEB TCNT_1 (read) H'FFF0 HICR MSTP2 = 0, HIE = 1 in SYSCR MSTP2
Section 26 List of Registers Lower Address H'FFF2 H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition KMPCR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR PORT TICRR MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y Register Name TCORA_Y H'FFF3 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR INT TICRF MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0
Section 26 List of Registers Lower Address Register Name H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Register Select Condition H8S/2160B, H8S/2161B Register Select Condition MSTP10 = 0 MSTP10 = 0 D/A Module Name H'FFF8 DADR0 H'FFF9 DADR1 H'FFFA DACR H'FFFC IDR_2 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR XBS TCONRI MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR Timer connection ODR_2 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR XBS TCONRO MSTP8 = 0
Section 27 Electrical Characteristics Section 27 Electrical Characteristics 27.1 Electrical Characteristics of H8S/2140B, H8S/2141B, H8S/2160B, and H8S/2161B 27.1.1 Absolute Maximum Ratings Table 27.1 lists the absolute maximum ratings. Table 27.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, VCL –0.3 to +4.3 V I/O buffer power supply voltage VCCB –0.3 to +7.
Section 27 Electrical Characteristics 27.1.2 DC Characteristics Table 27.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 27.3 and 27.4, respectively. Table 27.2 DC Characteristics (1) 9 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref* = 2.
Section 27 Electrical Characteristics Item Input high voltage Input low voltage Min Typ Max VIH VCC × 0.7 — AVCC + 0.3 V P97, P86, P52, P42 VCC × 0.7 — 5.5 Input pins except (1) and (2) above (Ports C to G are added in the H8S/2160B and H8S/2161B.) VCC × 0.7 — VCC + 0.3 –0.3 — VCC × 0.1 –0.3 — VCCB × 0.2 VCCB = 2.7 V to 4.0 V 0.8 VCCB = 4.0 V to 5.5 V VCC × 0.2 VCC = 2.7 V to 3.
Section 27 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOL — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA RESO — — 0.4 V IOL = 1.6 mA Item Output low voltage All output pins 5 (except RESO)* (Ports C to G are added in the H8S/2160B and H8S/2161B.) Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.
Section 27 Electrical Characteristics Table 27.2 DC Characteristics (2) 5 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Input leakage current Symbol Min Typ Max Unit Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 Port 7 — — 1.0 RES Test Conditions Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to AVCC – 0.
Section 27 Electrical Characteristics Item Normal operation Current 2 dissipation* Sleep mode 3 Standby mode* Symbol Min Typ Max Unit Test Conditions ICC — 30 40 mA f = 10 MHz — 20 32 mA f = 10 MHz — 1 5.0 µA — — 20.0 — 1.2 2.0 mA AlCC Ta ≤ 50°C 50°C < Ta Analog power supply current During A/D, D/A conversion Idle — 0.01 5.0 µA Reference power supply current During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 Idle — 0.01 5.
Section 27 Electrical Characteristics Table 27.2 DC Characteristics (3) When LPC Function Is Used Conditions: VCC = 3.0 V to 3.6 V, VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C Test Conditions Item Symbol Min Max Unit Input high voltage P37 to P30, P83 to P80, PB1, PB0 VIH VCC × 0.5 — V Input low voltage P37 to P30, P83 to P80, PB1, PB0 VIL — VCC × 0.
Section 27 Electrical Characteristics Table 27.3 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.
Section 27 Electrical Characteristics This LSI 600 Ω Ports 1 to 3 LED Figure 27.2 LED Drive Circuit (Example) Table 27.4 Bus Drive Characteristics Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Typ Max Unit VCC × 0.3 — — V — — VCC × 0.7 VCC = 2.7 V to 3.6 V VT – VT VCC × 0.05 — — VCC = 2.7 V to 3.6 V Input high voltage VIH VCC × 0.7 — 5.5 Input low voltage VIL –0.5 — VCC × 0.
Section 27 Electrical Characteristics Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Symbol Min Typ Max Unit Test Conditions Output low voltage VOL — — 0.8 V IOL = 16 mA, VCCB = 4.5 V to 5.5 V — — 0.5 IOL = 8 mA — — 0.4 IOL = 3 mA 27.1.3 AC Characteristics Figure 27.3 shows the test conditions for the AC characteristics.
Section 27 Electrical Characteristics Clock Timing: Table 27.5 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator. Table 27.5 Clock Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.
Section 27 Electrical Characteristics Control Signal Timing: Table 27.6 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 27.6 Control Signal Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions RES setup time tRESS 300 — ns Figure 27.
Section 27 Electrical Characteristics Bus Timing: Table 27.7 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 27.7 Bus Timing (1) (Normal Mode) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Address delay time tAD — 40 ns Address setup time tAS 0.
Section 27 Electrical Characteristics Table 27.7 Bus Timing (2) (Advanced Mode) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Address delay time tAD — 60 ns Address setup time tAS 0.5 × tcyc – 30 — ns Address hold time tAH 0.
Section 27 Electrical Characteristics Timing of On-Chip Peripheral Modules: Tables 27.8 to 27.11 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0 to 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 27.8 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 32.
Section 27 Electrical Characteristics Condition 10 MHz Item Symbol Min Max Unit Test Conditions Transmit data delay time (synchronous) tTXD — 100 ns Figure 27.24 Receive data setup time (synchronous) tRXS 100 — ns Receive data hold time (synchronous) tRXH 100 — ns A/D converter Trigger input setup time tTRGS 50 — ns Figure 27.25 WDT RESO output delay time tRESD — 200 ns Figure 27.
Section 27 Electrical Characteristics Table 27.9 Keyboard Buffer Controller Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Max Test Unit Conditions Notes 20 + 0.
Section 27 Electrical Characteristics Table 27.11 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Item LPC Symbol Min Typ Max Unit Test Conditions Input clock cycle tLcyc 30 — — ns Figure 27.
Section 27 Electrical Characteristics 27.1.4 A/D Conversion Characteristics Tables 27.12 and 27.13 list the A/D conversion characteristics. Table 27.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time — — 13.
Section 27 Electrical Characteristics Table 27.13 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VCCB = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time — — 13.
Section 27 Electrical Characteristics 27.1.5 D/A Conversion Characteristics Table 27.14 lists the D/A conversion characteristics. Table 27.14 D/A Conversion Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.
Section 27 Electrical Characteristics 27.1.6 Flash Memory Characteristics Table 27.15 shows the flash memory characteristics. Table 27.15 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Section 27 Electrical Characteristics 27.1.7 Usage Note The method of connecting an external capacitor is shown in figure 27.4. Connect the system power supply to the VCL pin together with the VCC pins. Vcc power supply VCL Bypass capacitor 10 µF 0.01 µF VSS < Vcc = 2.7 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins. It is recommended that a bypass capacitor be connected to the power supply pins. (Values are reference values.) Figure 27.
Section 27 Electrical Characteristics 27.2 Electrical Characteristics of H8S/2145B and H8S/2148B 27.2.1 Absolute Maximum Ratings Table 27.16 lists the absolute maximum ratings. Table 27.16 Absolute Maximum Ratings Item Symbol Value Unit 1 Power supply voltage* VCC –0.3 to +7.0 V I/O buffer power supply voltage (power supply for port A) VCCB –0.3 to +7.0 V Power supply voltage 1 (3-V version product)* VCC –0.3 to +4.3 V VCL –0.3 to +4.
Section 27 Electrical Characteristics Item Symbol Value Unit Operating temperature (flash memory programming/erasing) Topr Normal specification product: –20 to +75 °C Storage temperature Tstg Wide range temperature specification product: –40 to +85 –55 to +125 °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Ensure that for 5-V/4-V version products, the input pin voltage does not exceed 7.
Section 27 Electrical Characteristics 27.2.2 DC Characteristics Table 27.17 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 27.18 and 27.19, respectively. Table 27.17 DC Characteristics (1) 1 Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC* = 5.0 V ±10%, 1 1 AVref* = 4.
Section 27 Electrical Characteristics Item Input low voltage Symbol Min Typ Max Unit VIL –0.3 — 0.5 V PA7 to PA0 –0.3 — 1.0 NMI, EXTAL, input pins except (1) and (3) above –0.3 — 0.8 RES, STBY, MD1, MD0 (3) VCC – 0.5 — VCCB – 0.5 — V IOH = –200 µA 3.5 — — V IOH = –1 mA, 2.0 — — V IOH = –200 µA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.
Section 27 Electrical Characteristics 8. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC in output mode. Table 27.17 DC Characteristics (2) 1 Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC* = 5.0 V ±10%, 1 1 AVref* = 4.5 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Item Input leakage current Symbol Min Typ Max Unit Iin — — 10.
Section 27 Electrical Characteristics Item Reference power supply current Test Conditions Min Typ Max Unit During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 4.5 — 5.5 V Operating 2.0 — 5.5 2.0 — — 1 Analog power supply voltage* RAM standby voltage Symbol AVCC VRAM Idle/not used V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used.
Section 27 Electrical Characteristics Table 27.17 DC Characteristics (3) 1 Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Item Symbol – Schmitt P67 to P60 (KWUL (1) VT 2 6 trigger input = 00)* * , + VT 7 8 voltage KIN15 to KIN8* * , 3 IRQ2 to IRQ0* , + – VT – VT IRQ5 to IRQ3 Unit 1.0 — — V — — VCC × 0.
Section 27 Electrical Characteristics Symbol Min Typ Max Test Unit Conditions VIL –0.3 — 0.5 V –0.3 — 1.0 VCCB = 4.5 V to 5.5 V PA7 to PA0 –0.3 — 0.8 VCCB = 4.0 V to 4.5 V NMI, EXTAL, input pins except (1) and (3) above –0.3 — 0.8 Item Input low voltage RES, STBY, MD1, MD0 (3) — VCC – 0.5 VCCB – 0.5 — V IOH = –200 µA 3.5 — — V IOH = –1 mA, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V 3.0 — — V IOH = –1 mA, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V 1.
Section 27 Electrical Characteristics 5. 6. 7. 8. When the SCK0, SCK1, or SCK2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected.
Section 27 Electrical Characteristics Table 27.17 DC Characteristics (4) 1 Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Item Input leakage current Test Conditions Symbol Min Typ Max Unit Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 Port 7 — — 1.0 — — 1.0 µA Vin = 0.5 to VCC – 0.
Section 27 Electrical Characteristics Item Symbol Min Typ Max Unit AlCC — 1.2 2.0 mA Test Conditions Analog power supply current During A/D, D/A conversion Idle — 0.01 5.0 µA Reference power supply current During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 4.0 — 5.5 V Operating 2.0 — 5.5 2.0 — — Analog power supply voltage* RAM standby voltage 1 AVCC VRAM AVCC = 2.0 V to 5.
Section 27 Electrical Characteristics Table 27.17 DC Characteristics (5) 9 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref = 2.7 V to 3.
Section 27 Electrical Characteristics Item Input low voltage RES, STBY, MD1, MD0 (3) Symbol Min Typ Max Test Unit Conditions VIL –0.3 — VCC × 0.1 V –0.3 — VCCB × 0.2 VCCB = 2.7 V to 4.0 V 0.8 VCCB = 4.0 V to 5.5 V VCC × 0.2 VCC = 2.7 V to 3.6 V PA7 to PA0 –0.3 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, P86, 4 5 8 P52, and P42)* * * VOH VCC – 0.5 — VCCB – 0.5 — V IOH = –200 µA VCC – 1.0 — VCCB – 1.
Section 27 Electrical Characteristics 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB + 0.
Section 27 Electrical Characteristics Table 27.17 DC Characteristics (6) 5 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 1 AVref * = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Input leakage current RES Symbol Min Typ Max Unit Iin µA — — 10.0 STBY, NMI, MD1, MD0 — — 1.0 Port 7 — — 1.0 Test Conditions Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to AVCC – 0.
Section 27 Electrical Characteristics Item Reference power supply current Test Conditions Min Typ Max Unit During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 2.7 — 3.6 V Operating 2.0 — 3.6 2.0 — — 1 Analog power supply voltage* RAM standby voltage Symbol AVCC VRAM Idle/not used V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used.
Section 27 Electrical Characteristics Table 27.17 DC Characteristics (7) (3-V Version of H8S/2145BV) When LPC Function Is Used Conditions: VCC = 3.0 V to 3.6 V, VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref* = 2.7 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Input high voltage P37 to P30, P83 to P80, PB1, PB0 VIH VCC × 0.5 — V Input low voltage P37 to P30, P83 to P80, PB1, PB0 VIL — VCC × 0.
Section 27 Electrical Characteristics Table 27.18 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 27 Electrical Characteristics Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.
Section 27 Electrical Characteristics Table 27.19 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V version product), VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol – VT + VT Min Typ Max Unit VCC × 0.3 — — V — — VCC × 0.7 Test Conditions VT – VT VCC × 0.05 — — Input high voltage VIH VCC × 0.7 — 5.5 Input low voltage VIL –0.5 — VCC × 0.
Section 27 Electrical Characteristics 27.2.3 AC Characteristics The following shows the clock timing, control signal timing, bus timing, and on-chip peripheral function timing. For the AC characteristics test conditions, see figure 27.3. Clock Timing: Table 27.20 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.
Section 27 Electrical Characteristics Control Signal Timing: Table 27.21 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 27.21 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.
Section 27 Electrical Characteristics Bus Timing: Table 27.22 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 27.22 Bus Timing (1) (Normal Mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 27 Electrical Characteristics Condition A Condition B Condition C 10 MHz 16 MHz 20 MHz Test Unit Conditions Item Symbol Min Max Min Max Min Max Read data access time 3 tACC3 — 2.0 × tcyc – 60 — 2.0 × tcyc – 40 — 2.0 × ns tcyc – 30 Read data access time 4 tACC4 — 2.5 × tcyc – 50 — 2.5 × tcyc – 35 — 2.5 × ns tcyc – 25 Read data access time 5 tACC5 — 3.0 × tcyc – 60 — 3.0 × tcyc – 40 — 3.
Section 27 Electrical Characteristics Table 27.22 Bus Timing (2) (Advanced Mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 27 Electrical Characteristics Condition A Condition B Condition C 10 MHz 16 MHz 20 MHz Test Unit Conditions Item Symbol Min Max Min Max Min Max Read data access time 4 tACC4 — 2.5 × tcyc – 50 — 2.5 × tcyc – 35 — 2.5 × ns tcyc – 25 Read data access time 5 tACC5 — 3.0 × tcyc – 80 — 3.0 × tcyc – 55 — 3.0 × ns tcyc – 40 HWR, LWR delay time 1 tWRD1 — 60 — 45 — 30 ns HWR, LWR delay time 2 tWRD2 — 60 — 45 — 30 ns HWR, LWR pulse width 1 tWSW1 — 1.
Section 27 Electrical Characteristics Timing of On-Chip Peripheral Modules: Tables 27.23 to 27.26 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 27.23 Timing of On-Chip Peripheral Modules (1) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 27 Electrical Characteristics Timer clock pulse width Condition B Condition C 10 MHz 16 MHz 20 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Single edge tTMCWH 1.5 — 1.5 — 1.5 — tcyc Figure 27.20 Both edges tTMCWL 2.5 — 2.5 — 2.5 — Item TMR Condition A PWM, PWMX Pulse output delay time tPWOD — 100 — 50 — 50 ns Figure 27.22 SCI Input clock cycle tScyc 4 — 4 — 4 — tcyc Figure 27.
Section 27 Electrical Characteristics Table 27.23 Timing of On-Chip Peripheral Modules (2) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 27 Electrical Characteristics Table 27.24 Keyboard Buffer Controller Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3-V product), VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Max Test Unit Conditions Notes 20 + 0.
Section 27 Electrical Characteristics Table 27.26 LPC Module Timing (For H8S/2145B Only) Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Item LPC Symbol Min Typ Max Unit Test Conditions Input clock cycle tLcyc 30 — — ns Figure 27.
Section 27 Electrical Characteristics 27.2.4 A/D Conversion Characteristics Tables 27.27 and 27.28 list the A/D conversion characteristics. Table 27.27 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.
Section 27 Electrical Characteristics Table 27.28 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 27 Electrical Characteristics 27.2.5 D/A Conversion Characteristics Table 27.29 lists the D/A conversion characteristics. Table 27.29 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 27 Electrical Characteristics 27.2.6 Flash Memory Characteristics Table 27.30 shows the flash memory characteristics. Table 27.30 Flash Memory Characteristics (Operation Range at Programming/Erasing) 5-V version conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (normal specification product), Ta = –40 to +85°C (wide range temperature specification product) 3-V version conditions: VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Section 27 Electrical Characteristics Vcc power supply External capacitor for power supply regulation 0.47 µF (one, or two in parallel) Bypass capacitor VCL Product with internal step-down function 10 µF VCL Product without internal step-down function 0.01 µF VSS VSS The VCC power supply should not be connected to the VCL pin of the product with the internal step-down function. (Connect the VCC power supply to other VCC1 pins as usual.
Section 27 Electrical Characteristics 27.3 Timing Chart 27.3.1 Clock Timing The clock timings are shown below. tcyc tCH tCf φ tCL tCr Figure 27.6 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 RES φ Figure 27.7 Oscillation Settling Timing Rev. 3.
Section 27 Electrical Characteristics φ NMI IRQi tOSC2 Note: i = 0 to 2, 6, 7 Figure 27.8 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 3.
Section 27 Electrical Characteristics 27.3.2 Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 27.9 Reset Input Timing φ tNMIH tNMIS NMI tNMIW IRQi tIRQW tIRQS tIRQH IRQi Edge input tIRQS IRQi Level input Note: i = 7 to 0 Figure 27.10 Interrupt Input Timing Rev. 3.
Section 27 Electrical Characteristics 27.3.3 Bus Timing The bus timings are shown below. T1 T2 φ tAD A23 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.11 Basic Bus Timing (Two-State Access) Rev. 3.
Section 27 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0, IOS* tCSD tAS tASD tAH tASD AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.12 Basic Bus Timing (Three-State Access) Rev. 3.
Section 27 Electrical Characteristics T1 T2 TW T3 φ A23 to A0, IOS* AS* RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.13 Basic Bus Timing (Three-State Access with One Wait State) Rev. 3.
Section 27 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0, IOS* tAS tASD tASD tAH AS* tRSD2 RD (read) tACC3 tRDS D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.14 Burst ROM Access Timing (Two-State Access) Rev. 3.
Section 27 Electrical Characteristics T1 T2 or T3 T1 φ tAD A23 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 27.15 Burst ROM Access Timing (One-State Access) Rev. 3.
Section 27 Electrical Characteristics 27.3.4 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. T1 T2 φ tPRS Ports 1 to 9, A, and B (Ports C to G are added in H8S/2160B and H8S/2161B) (read) tPRH tPWD Ports 1 to 6, 8, 9, A, and B (Ports C to F are added in H8S/2160B and H8S/2161B) (write) Figure 27.16 I/O Port Input/Output Timing φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 27.17 FRT Input/Output Timing Rev. 3.
Section 27 Electrical Characteristics φ tFTCS FTCI tFTCWL tFTCWH Figure 27.18 FRT Clock Input Timing φ tTMOD TMO0, TMO1 TMOX Figure 27.19 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 27.20 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 27.21 8-Bit Timer Reset Input Timing Rev. 3.
Section 27 Electrical Characteristics φ tPWOD PW15 to PW0, PWX1, PWX0 Figure 27.22 PWM, PWMX Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 27.23 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 27.24 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 27.25 A/D Converter External Trigger Input Timing Rev. 3.
Section 27 Electrical Characteristics φ tRESD tRESD RESO tRESOW Figure 27.26 WDT Output Timing (RESO RESO) RESO Host interface (XBS) read timing CS/HA0 tHAR tHRPW tHRA IOR tHRD HDB7 to HDB0 tHRF Valid data tHIRQ HIRQi* Notes: i = 1, 11, 12, 3, 4 * The rising edge timing is the same as the port 4 and port B output timing. See figure 28.16. Host interface (XBS) write timing CS/HA0 tHAW tHWPW tHWA IOW tHDW tHWD HDB7 to HDB0 tHGA GA20 Figure 27.27 Host Interface (XBS) Timing Rev. 3.
Section 27 Electrical Characteristics 1. Reception φ tKBIS tKBIH KCLK/ KD 2. Transmission (a) T1 T2 φ tKBOD KCLK/ KD Transmission (b) KCLK/ KD tKBF Legend: KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Note: φ shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. Figure 27.28 Keyboard Buffer Controller Timing Rev. 3.
Section 27 Electrical Characteristics VIH SDA0, SDA1 VIL tBUF tSTAH SCL0, SCL1 P* tSCLH tSTAS S* tSf tSP tSTOS Sr* tSCLL P* tSDAS tSr tSCL tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 27.
Section 27 Electrical Characteristics Testing voltage: 0.4Vcc 50pF Figure 27.31 Tester Measurement Condition Rev. 3.
Appendix A I/O Port States in Each Processing State Appendix A I/O Port States in Each Processing State Table A.
Appendix A I/O Port States in Each Processing State Port Name Pin Name MCU Operating Mode Reset Hardware Software Standby Standby Mode Mode Port 96 φ EXCL 1 Clock output T 2, 3 (EXPE = 1) T Watch Mode [DDR = 1] H EXCL input [DDR = 0] T H Subactive Mode Program Execution State EXCL input EXCL input Clock output/ EXCL input/ input port T H H H H AS, HWR, RD AS, HWR, RD T 2, 3 (EXPE = 0) Ports 92, 91 [DDR = 1] clock output Subsleep Mode [DDR = 0] T 2, 3 (EXPE = 0) Ports 95 to 93 1
Appendix B Product Codes Appendix B Product Codes Product Type Product Code Mark Code Package (Package Code) 144-pin TQFP (TFP-144) H8S/2161B Flash memory version (3-V version) HD64F2161BV F2161BVTE10 H8S/2160B Flash memory version (3-V version) HD64F2160BV F2160BVTE10 H8S/2141B Flash memory version (3-V version) HD64F2141BV F2141BVFA10 F2141BVTE10 100-pin TQFP (TFP-100B) H8S/2140B Flash memory version (3-V version) HD64F2140BV F2140BVFA10 100-pin QFP (FP-100B) F2140BVTE10 100-pin TQ
Appendix C Package Dimensions Appendix C Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 50 bp c c1 HE *2 E b1 ZE Terminal cross section 26 100 1 25 c F A2 A ZD θ A1 L L1 Detail F e *3 y bp x M Figure C.1 Package Dimensions (FP-100B) Rev. 3.
Appendix C Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 75 51 76 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix C Package Dimensions JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 72 HE b1 c c1 *2 E bp ZE Reference Dimension in Millimeters Symbol 37 144 Terminal cross section 1 36 ZD Index mark c A2 A F θ *3 y bp L A1 e x M L1 Detail F Figure C.3 Package Dimensions (TFP-144) Rev. 3.
Index Index 14-Bit PWM Timer (PWMX) ................. 243 16-Bit Count Mode ................................. 305 16-Bit Free-Running Timer (FRT) ......... 259 Burst ROM Interface...............................141 Bus Arbitration........................................144 Bus Controller (BSC)..............................121 2fH Modification .................................... 334 Cascaded Connection ..............................305 CBLANK Output ....................................
Index DTVECR ................ 151, 663, 673, 682, 692 EBR1 ...................... 614, 664, 674, 683, 692 EBR2 ...................... 614, 664, 674, 683, 692 EEPMOV Instruction................................ 61 Effective Address ..................................... 55 Effective address extension ...................... 50 Erase/Erase-Verify.................................. 626 erasing units............................................ 608 ERI..........................................................
Index LADR3 ................... 543, 661, 671, 680, 690 Logic Operations Instructions................... 45 LPWRCR................ 644, 664, 674, 683, 692 Mark State............................................... 406 MCU Operating Mode Selection .............. 63 MDCR....................... 64, 667, 676, 685, 696 Medium-Speed Mode ............................. 649 Memory Indirect ....................................... 54 Module Stop Mode ................................. 656 MRA ..........................
Index Power-Down Modes ............................... 641 Program Counter (PC) .............................. 35 Program/Erase Protection ....................... 628 Program/Program-Verify ........................ 624 Program-Counter Relative ........................ 54 Programmer Mode.................................. 630 Pulse Output ........................................... 271 PWDPR .................. 236, 668, 677, 686, 697 PWDR..................... 236, 668, 677, 686, 697 PWM Decoding ............
Index Trap Instruction Exception Handling........ 85 TSR......................................................... 362 TWR ....................... 545, 660, 671, 680, 689 TXI.......................................................... 405 User Program Mode................................ 622 Wait Control............................................139 Watch Mode............................................653 Watchdog Timer (WDT).........................345 Watchdog Timer Mode ...........................
Index Rev. 3.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2140B Group Publication Date: 1st Edition, March 2002 Rev.3.00, March 21, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2140B Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0300-0300