Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 167 of 788
REJ09B0300-0300
Section 8 I/O Ports
8.1 Overview
This LSI has ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7).
For additional ports C to G in H8S/2160B and H8S/2161B, see section 8.13 Additional Overview
for H8S/2160B and H8S/2161B.
Table 8.1 is a summary of the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only port) and data registers (DR, ODR) that store output data.
Ports 1 to 3, 6, A, and B have an on-chip input pull-up MOS function. For ports A and B, the
on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an
input pull-up MOS control register (PCR), in addition to DDR, to control the on/off status of the
input pull-up MOS.
Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O
ports can drive a Darlington transistor when in output mode. Ports 1 to 3 can drive an LED (10
mA sink current).
Port A input and output use by the VccB power supply, which is independent of the V
CC
power
supply. When the VccB voltage is 5V, the pins on port A will be 5-V tolerant.
PA4 to PA7 of port A have bus-buffer drive capability.
P52 in port 5, P97 in port 9, P86 in port 8 and P42 in port 4 are NMOS push-pull outputs. P52,
P97, P86 and P42 are thus 5-V tolerant, with DC characteristics that are dependent on the V
CC
voltage.
For the P42/SCK2, P52/SCK0, P86/SCK1, and P97 outputs, connect pull-up resistors to pins to
raise output-high-level voltage.