Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 288 of 788
REJ09B0300-0300
Figures 12.1 and 12.2 show block diagrams of the 8-bit timer module.
TMR_X and TMR_Y have a similar configuration, but cannot be cascaded. TMR_X also has an
input capture function. For details, see section 13, Timer Connection.
External clock
sources
Internal clock
sources
TMR_0
φ/2, φ/8
φ/32, φ/64
φ/256, φ/1024
Clock 1
Clock 0
Compare-match A1
Compare-match A0
Clear 1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
TMO0
TMRI0
Internal bus
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare-match B1
Compare-match B0
TMO1
TMRI1
Clock select
Control logic
Clear 0
TMR_1
φ/2, φ/8
φ/64, φ/128
φ/1024, φ/2048
Legend:
TCORA_0
TCORB_0
TCNT_0
TCSR_0
TCR_0
: Time constant register A_0
: Time constant register B_0
: Timer counter_0
: Timer control/status register_0
: Timer control register_0
TCORA_1
TCORB_1
TCNT_1
TCSR_1
TCR_1
: Time constant register A_1
: Time constant register B_1
: Timer counter_1
: Timer control/status register_1
: Timer control register_1
Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)