Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1064 of 1130
REJ09B0327-0400
TCSR0—Timer Control/Status Register 0 H'FFCA TMR0
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR0
Output select 1 and 0
0 No change at compare match A
0
0 output at compare match A1
1 1 output at compare match A0
Output inverted at compare
match A (toggle output)
1
Note:
Output select 3 and 2
0 No change at compare match B
0
0 output at compare match B1
1 1 output at compare match B0
Output inverted at compare
match B (toggle output)
1
A/D trigger enable
0 A/D converter start requests by compare match A
are disabled
1 A/D converter start requests by compare match A
are enabled
Timer overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
* Only 0 can be written in bits 7 to 5, to clear the flags.