Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 126 of 1130
REJ09B0327-0400
5.3 Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts.
5.3.1 External Interrupts
There are nine external interrupt sources from 25 input pins (23 actual pins): NMI, IRQ7 to IRQ0,
and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the
IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6
,
and IRQ2 to IRQ0 can be used to restore the
H8S/2148 Group or H8S/2144 Group chip from software standby mode.
NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt
control mode and the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be
used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts
Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to
IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt control level can be set with ICR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.