Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 360 of 1130
REJ09B0327-0400
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IS
0
R/W
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the
counter.
TISR is initialized to H'FE by a reset and in hardware standby mode.
Bits 7 to 1—Reserved: Do not write 0 to these bits.
Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer
clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source
for the counter.
Bit 0
IS Description
0 IVG signal is selected (H8S/2148 Group) (Initial value)
External clock/reset input is disabled (H8S/2144 Group and H8S/2147N)
1 VSYNCI/TMIY (TMCIY/TMRIY) is selected