To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Rev. 4.
Preface The H8S/2148 Group, H8S/2144 Group, and H8S/2147N comprise high-performance microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen internal 16-bit general registers with a 32-bit configuration, and a concise and optimized instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
This manual describes the hardware of the H8S/2148 Group, H8S/2144 Group, and H8S/2147N. Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of the instruction set. Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
Main Revisions for This Edition Item Page Revision (See Manual for Details) All — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8S/2148 Series → (After) H8S/2148 Group (Before) H8S/2144 Series → (After) H8S/2144 Group 1.1 Overview 4 Host interface specification in table 1.1 amended • 8-bit host interface (ISA) port Table 1.1 Overview 6 Product lineup specification in table 1.
Item Page Revision (See Manual for Details) 1.3.2 Pin Functions in Each Operating Mode 14 Mode 1 description of pin 35 amended Table 1.2 (a) Pin Functions in Each Operating Mode Table 1.
Item Page Revision (See Manual for Details) 5.2.8 Address Break Control Register (ABRKCR) 124 Read/Write description amended 5.5.3 Interrupt control Mode 1 140 Bit 7 (Before) R/W → (After) R (Before) Only NMI interrupts enabled and address break → (After) Only NMI interrupts and address break enabled Figure 5.9 Example of State Transitions in Interrupt control Mode 1 8.1 Overview Figure 5.9 amended 213 Table 8.1 H8S/2148 Group Port Functions Table 8.
Item Page Revision (See Manual for Details) 8.1 Overview 220 Table 8.3 amended Table 8.3 H8S/2144 Port Functions Expanded Modes Port Port A 8.7.2 Register Configuration 247 Table 8.
Item Page Revision (See Manual for Details) 8.11.3 Pin Functions 270 Table 8.23 amended Table 8.23 Port A Pin Functions Pin Selection Method and Pin Functions PA1/A17/KIN9/ CIN9 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Item Page Revision (See Manual for Details) 16.1.1 Features 492 • Automatic switching from formatless mode to I C bus format (channel 0 only) 2 Description added 16.4 Usage Notes 548 Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Figure 16.
Item Page Revision (See Manual for Details) 22.4.2 Block Diagram 643 Figure 22.2 amended Figure 22.2 Block Diagram of Flash Memory Internal address bus Internal data bus (16 bits) Module bus FLMCR1 * FLMCR2 * EBR1 EBR2 Operating mode Bus interface/controller Mode pins * * Flash memory (128 kbytes/64 kbytes) 22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) 653 22.10.
Item Page Revision (See Manual for Details) 22.10.4 Memory Read Mode 676 Figure 22.19 amended FA17 to FA0 Figure 22.19 Timing Waveforms for CE/OE Clocked Read Address stable Address stable tacc CE tce tce OE toe toe WE tdf tdf tacc FO7 to FO0 Data Data toh 22.10.7 Status Read Mode 681 toh Figure 22.22 amended CE Figure 22.22 Status Read Mode Timing Waveforms tnxtc tce OE WE 699 tnxtc twep tceh tces tf 23.5.
Item Page Revision (See Manual for Details) 23.6.1 Boot Mode 705 Description amended H'(FF)E088 and above 23.7.2 Program-Verify Mode 710 Figure 23.12 Program/Program-Verify Flowcharts Note *6 added to figure 23.
Item Page Revision (See Manual for Details) 23.10.4 Memory Read Mode 722 Figure 23.19 amended FA17 to FA0 Figure 23.19 Timing Waveforms for CE/OE Clocked Read Address stable Address stable tacc CE tce tce OE toe toe WE FO7 to FO0 Data Data toh 23.10.5 Auto-Program Mode 724 toh Figure 23.20 amended Address stable FA17 to FA0 Figure 23.
Item Page Revision (See Manual for Details) 23.10.7 Status Read Mode 727 Figure 23.22 amended CE Figure 23.22 Status Read Mode Timing Waveforms WE tnxtc twep tceh tces tf tnxtc twep tceh tces tf tr toe tdf tr tds tds tdh tdh 24.7 Subclock Input Circuit 740 25.12 Usage Notes 764 Section 25.12 added 26.2.6 Flash Memory Characteristics 799 Table 26.15 amended Table 26.
Item Page Revision (See Manual for Details) 26.3.4 A/D Conversion Characteristics 831 Note *4 added to table condition 4 4 Condition C: VCC = 3.0 V to 3.6V* , AVCC = 3.0 V to 3.6 V* , 4 4 * * AVref = 3.0 V to AVCC , VCCB = 3.0 V to 5.5 V , ... Table 26.27 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266State Conversion) 26.3.6 Flash Memory Characteristics Note 4 amended Note: 4. When using CIN, the applicable range is VCC = 3.0 V to 3.6 V, ... 833 Table 26.
Item Page Revision (See Manual for Details) 26.4.6 Flash Memory Characteristics 862 Table 26.43 amended Item Table 26.43 Flash Memory Characteristics (Programming/erasing operating range) Symbol Reprogramming count Data retention time*10 Programming Wait time after SWE-bit setting* 863 1 Typ NWEC Min 100*8 Max 10000*9 — Unit tDRP 10 — — Years x 10 — — µs Test Condition Times Notes 8 to 10 added Notes: 8.
Item Page Revision (See Manual for Details) 26.6.6 Flash Memory Characteristics 908 Table 26.67 amended Symbol of wait time after SWE-bit clear (Before) Θ → (After) θ Table 26.67 Flash Memory Characteristics (Programming/erasing operating range) 909 Min 100*8 Typ Max 10000*9 — Test Condition Item Symbol Reprogramming count NWEC Unit Data retention time*10 tDRP 10 — — Years Programming Wait time after SWE-bit setting*1 x 1 — — µs Times Notes 8 to 10 added Notes: 8.
Item Page Revision (See Manual for Details) A.1 Instruction 930 Table A.1 amended Table A.1 Instruction Set 2. Arithmetic Instructions EXTU TAS 933 Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @(d,ERn) @ERn Rn #xx Size Mnemonic @-ERn/@ERn+ Addressing Mode and Instruction Length (Bytes) EXTU.W Rd W 2 0 → ( of Rd16) — — 0 0 — 1 EXTU.
Item Page Revision (See Manual for Details) B.
Item Page Revision (See Manual for Details) B.
Item Page Revision (See Manual for Details) B.3 Functions 1077 TICRRH'FFF2 TMRX TICRFH'FFF3 TMRX Figure amended (Before) Stores TCNT value at fall of external trigger input → (After) Stores TCNT value at fall of external reset input 1080 STR1H'FFF6 HIF STR2H'FFFE HIF Slave R/W description amended Bit 0 (Before) R → (After) R/(W) C.2 Port 2 Block Diagrams 1089 Figure C.4 amended Figure C.
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Arrangement and Functions............................................................................
2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.
Section 5 Interrupt Controller .......................................................................................... 113 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ........................................................................
Section 6 Bus Controller ................................................................................................... 151 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram .....................................................................
7.3 7.4 7.5 7.2.4 DTC Destination Address Register (DAR).......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR)..........................................
8.5.2 Register Configuration......................................................................................... 8.5.3 Pin Functions ....................................................................................................... 8.6 Port 5................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.
9.3 9.2.1 PWM Register Select (PWSL)............................................................................. 9.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 9.2.5 Peripheral Clock Select Register (PCSR) ............................................................ 9.2.
11.2.7 Timer Control/Status Register (TCSR) ................................................................ 11.2.8 Timer Control Register (TCR) ............................................................................. 11.2.9 Timer Output Compare Control Register (TOCR) .............................................. 11.2.10 Module Stop Control Register (MSTPCR) .......................................................... Operation ...........................................................................
12.3.2 Compare-Match Timing....................................................................................... 12.3.3 TCNT External Reset Timing .............................................................................. 12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 12.3.5 Operation with Cascaded Connection.................................................................. 12.3.6 Input Capture Operation ......................................
14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 14.2.
15.3 Operation .......................................................................................................................... 15.3.1 Overview.............................................................................................................. 15.3.2 Operation in Asynchronous Mode ....................................................................... 15.3.3 Multiprocessor Communication Function............................................................ 15.3.
17.1.1 Features................................................................................................................ 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Input/Output Pins ................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 601 18.5 Usage Note........................................................................................................................ 603 Section 19 D/A Converter ................................................................................................. 605 19.1 Overview........................................................................................................................... 19.1.
21.3 Operation .......................................................................................................................... 637 21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1)) ...................................................... 637 21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 637 Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) ..................................................
22.10.4 Memory Read Mode ............................................................................................ 22.10.5 Auto-Program Mode ............................................................................................ 22.10.6 Auto-Erase Mode................................................................................................. 22.10.7 Status Read Mode ................................................................................................ 22.10.8 Status Polling .........
23.8.3 Error Protection.................................................................................................... 23.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 23.10 Flash Memory Programmer Mode .................................................................................... 23.10.1 Programmer Mode Setting ................................................................................... 23.10.2 Socket Adapters and Memory Map ............
25.3 Medium-Speed Mode........................................................................................................ 25.4 Sleep Mode ....................................................................................................................... 25.4.1 Sleep Mode .......................................................................................................... 25.4.2 Clearing Sleep Mode............................................................................................ 25.
26.3 Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version), H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of H8S/2148 and H8S/2147.................................................................................................................... 26.3.1 Absolute Maximum Ratings ................................................................................ 26.3.2 DC Characteristics ............................................................................................... 26.3.
26.7.5 Timing of On-Chip Supporting Modules............................................................. 919 Appendix A Instruction Set .............................................................................................. 925 A.1 A.2 A.3 A.4 A.5 Instruction ......................................................................................................................... Instruction Codes .......................................................................................................
Rev. 4.
Section 1 Overview Section 1 Overview 1.1 Overview This LSI comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Section 1 Overview Table 1.
Section 1 Overview Item Specifications Bus controller • 2-state or 3-state access space can be designated for external expansion areas • Number of program wait states can be set for external expansion areas • Can be activated by internal interrupt or software • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc.
Section 1 Overview Item Specifications 14-bit PWM timer (PWMX) • Up to 2 outputs • Resolution: 1/16384 • 312.5 kHz maximum carrier frequency (20-MHz operation) Serial communication • interface • (SCI: 2 channels, SCI0 and SCI1) Asynchronous mode or synchronous mode selectable • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Compatible with IrDA specification version 1.
Section 1 Overview Item Specifications D/A converter • Resolution: 8 bits • Output: 2 channels • 74 input/output pins (including 24 with LED drive capability) • 8 input-only pins • VCCB (separate power supply) drive pins among I/O pins (H8S/2148 Group and H8S/2147N) • Flash memory or mask ROM • High-speed static RAM I/O ports Memory Interrupt controller Power-down state Product Name ROM RAM H8S/2144, H8S/2148 128 kbytes 4 kbytes H8S/2143 96 kbytes 4 kbytes H8S/2142, H8S/2147, H
Section 1 Overview Item Specifications Product Code*2 Product lineup (preliminary) Group Mask ROM Versions F-ZTAT Versions ROM/RAM (Bytes) H8S/2148 HD6432148S HD64F2148 HD64F2148V*2 128 k/4 k HD6432148SW*1 HD64F2148A HD64F2148AV*2 HD6432147S HD64F2147A HD6432147SW*1 HD64F2147AV*2 H8S/2147N — HD64F2147N HD64F2147NV*2 64 k/2 k H8S/2144 HD6432144S HD64F2144 HD64F2144V*2 128 k/4 k Packages FP-100B, TFP-100B 64 k/2 k HD64F2144A HD64F2144AV*2 HD6432143S — 96 k/4 k HD6432142 HD64F2142
Section 1 Overview 1.2 Internal Block Diagram VCC1 VCC2 (VCL) VSS VSS VSS VSS VSS An internal block diagram of the H8S/2148 Group is shown in figure 1.1 (a), an internal block diagram of the H8S/2147N is shown in figure 1.1 (b), and an internal block diagram of the H8S/2144 Group in figure 1.1 (c).
P51/RxD0 P50/TxD0 Port A Bus controller Internal data bus Internal address bus VSS VSS VSS Port 2 Port 9 Port 1 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7 Port 3 14-bit PWM 8-bit timer × 3ch (TMR0, TMR1, TMRY) Host interface 10-bit A/D SCI × 3ch (IrDA × 1ch) Port B P52/SCK0/SCL0 8-bit PWM 16-bit FRT 8-bit D/A IIC × 2ch (option) P77/AN7/DA1 P76/AN6/DA0 P75/AN5 Port 7 AVref AVCC AVSS P82/HIFSD P81/CS2/GA20 P80/HA0 P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84
Port A Port 9 Interrupt controller P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG Port 1 WDT0, WDT1 RAM Port 6 14-bit PWM 8-bit timer × 3ch (TMR0, TMR1, TMRY) SCI × 3ch (IrDA × 1ch) Port B 10-bit A/D 8-bit D/A Port 5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 P37/D15 P36/D14 P35/D13 P34/D12 P33/D11 P32/D10 P31/D9 P30/D8 PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0 P70/AN0 P73/AN3 P72/AN2 P71/AN1 AVSS P77/AN7/DA1 P76/AN6/DA0 Port 7 AVref AVCC P82 P81 P80 P84/IRQ3/TxD1 P83 P86/IRQ5/SCK1 P85/IR
Section 1 Overview 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement P42/TMRI0/SCK2/SDA1 P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P45/TMRI1/HIRQ12/CSYNCI P46/PWX0 P47/PWX1 PB7/D7 PB6/D6 VCC1 P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB5/D5 PB4/D4 VSS VSS P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 The pin arrangement of the H8S/2148 Group is shown in figure 1.
P42/TMRI0/SCK2/SDA1 P43/TMCI1/HIRQ11 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ12 P46/PWX0 P47/PWX1 PB7/D7 PB6/D6 VCC1 P27/A15/PW15 P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB5/D5 PB4/D4 VSS VSS P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 Section 1 Overview PW3/A3/P13 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 P41/TMO0/RxD2/IrRxD PW2/A2/P12 77 49 P40/TMCI0/TxD2/IrTxD PW1/A1/P11 78 48 PA0/A16/CIN8/KIN8
P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 PB7/D7 PB6/D6 VCC1 P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 PB5/D5 PB4/D4 VSS VSS P17/A7 P16/A6 P15/A5 P14/A4 Section 1 Overview A3/P13 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 P41/TMO0/RxD2/IrRxD A2/P12 77 49 P40/TMCI0/TxD2/IrTxD A1/P11 78 48 PA0/A16/CIN8/KIN8 A0/P10 79 47 PA1/A17/CIN9/KIN9 D3/PB3 80 46 AVSS D2/PB2 81 45 P77/AN7/DA1 D8/P
Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Tables 1.2 (a), (b) and (c) show the pin functions of the H8S/2148 Group, H8S/2147N, and H8S/2144 Group in each of the operating modes. Table 1.2 (a) H8S/2148 Group Pin Functions in Each Operating Mode Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No. FP-100B TFP-100B Expanded Modes Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Flash Memory Writer Mode 94 P81 P81 P81/CS2/GA20 NC 95 P82 P82 P82/HIFSD NC 96 P83 P83 P83 NC 97 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC 98 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC 99 P86/IRQ5/SCK1/ P86/IRQ5/SCK1/ SCL1 SCL1 P86/IRQ5/SCK1/ SCL1 NC 100 RESO RESO NC RESO Rev. 4.
Section 1 Overview Table 1.2 (b) H8S/2147N Pin Functions in Each Operating Mode Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Table 1.2 (c) H8S/2144 Group Pin Functions in Each Operating Mode Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview Pin Name Pin No.
Section 1 Overview 1.3.3 Pin Functions Table 1.3 summarizes the pin functions of this LSI. Table 1.3 Pin Functions Pin No. Type Symbol Power supply VCC1 Clock FP-100B TFP-100B I/O Name and Function Power supply: For connection to the power supply. All VCC1 and VCC2* pins should be connected to the system power supply.
Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B Operating mode control MD1 MD0 5 6 I/O Name and Function Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD1 and MD0 and the operating mode is shown below. These pins should not be changed while the MCU is operating.
Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B I/O Name and Function Bus control WAIT 16 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. RD 22 Output Read: When this pin is low, it indicates that the external address space is being read. HWR 19 Output High write: When this pin is low, it indicates that the external address space is being written to. The upper half of the data bus is valid.
Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B 8-bit timer (TMR0, TMR1, TMRX, TMRY) TMO0 TMO1 TMOX 50 53 35 Output Compare-match output: TMR0, TMR1, and TMRX compare-match output pins. TMCI0 TMCI1 49 52 Input Counter external clock input: Input pins for the external clock input to the TMR0 and TMR1 counters. TMRI0 TMRI1 51 54 Input Counter external reset input: TMR0 and TMR1 counter reset input pins.
Section 1 Overview Pin No. Type Symbol Host interface (HIF) HDB7 to HDB0 FP-100B TFP-100B I/O Name and Function 89 to 82 Input/ output Host interface data bus: Bidirectional 8-bit bus for accessing the host interface. CS1, CS2, ECS2 CS3, CS4 18, 94, 25 81, 80 Input Chip select 1, 2, 3, and 4: Input pins for selecting host interface channel 1 to 4. IOR 22 Input I/O read: Input pin that enables reading from the host interface.
Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B D/A converter (DAC) DA0 DA1 44 45 Output Analog output: D/A converter analog output pins. A/D converter AVCC 37 Input I/O D/A converter Name and Function Analog reference voltage: The analog power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+5 V or +3 V).
Section 1 Overview Pin No. Type Symbol I/O ports P17 to P10 FP-100B TFP-100B I/O Name and Function 72 to 79 Input/ output Port 1: Eight input/output pins. The data direction of each pin can be selected in the port 1 data direction register (P1DDR). These pins have built-in MOS input pull-ups, and also have LED drive capability. P27 to P20 60 to 67 Input/ output Port 2: Eight input/output pins. The data direction of each pin can be selected in the port 2 data direction register (P2DDR).
Section 1 Overview Pin No. Type Symbol I/O ports PA7 to PA0 PB7 to PB0 Note: * FP-100B TFP-100B I/O Name and Function 10, 11, 20, 21, 30, 31, 47, 48 Input/ output Port A: Eight input/output pins. The data direction of each pin can be selected in the port A data direction register (PADDR). These pins have built-in MOS input pull-ups. These are the VCCB drive pins. [H8S/2148 Group and H8S/2147N only] 57, 58, 68, 69, 80, 81, 90, 91 Input/ output Port B: Eight input/output pins.
Section 1 Overview Rev. 4.
Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
Section 2 CPU • High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 20 MHz 8/16/32-bit register-register add/subtract: 50 ns 8 × 8-bit register-register multiply: 600 ns 16 ÷ 8-bit register-register divide: 600 ns 16 × 16-bit register-register multiply: 1000 ns 32 ÷ 16-bit register-register divide: 1000 ns • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction
Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller.
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling.
Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch (b) Exception Handling Note: * Ignored when returning. Figure 2.
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling.
Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) (a) Subroutine Branch CCR SP PC (24 bits) (b) Exception Handling Figure 2.
Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.6 Memory Map Rev. 4.
Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers.
Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Section 2 CPU 2.4.4 Initial Register Values Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 4.
Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Word data En Data Format 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Rev. 4.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.
Section 2 CPU Instruction Rn @ERn @(d:16,ERn) @(d:32, ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8, PC) @(d:16, PC) @@aa:8 System control TRAPA — — — — — — — — — — — — — RTE — — — — — — — — — — — — — SLEEP — — — — — — — — — — — — — — Function #xx Addressing Modes LDC B B W W W W — W — W — — — — STC — B W W W W — W — W — — — — ANDC, ORC, XORC B — — — — — — — — — — — — — NOP Block data transfer — —
Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. 1 POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Section 2 CPU Type Instruction Size* Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Type Instruction Size* Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Type Instruction Size* Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. 1 The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Type Instruction Size* Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Type Instruction Size* Function System control instructions TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. 1 SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Type Instruction Size* Function Block data transfer instructions EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; 1 Block transfer instruction. Transfers the number of data bytes specified by R4L or R4 from locations starting at the address indicated by ER5 to locations starting at the address indicated by ER6. After the transfer, the next instruction is executed.
Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.12 Instruction Formats (Examples) 2.6.
Section 2 CPU absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 Addressing Modes No.
Section 2 CPU Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
Section 2 CPU Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bitmanipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.
Section 2 CPU Table 2.6 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct (Rn) op 2 Effective Address Calculation Effective Address (EA) Operand is general register contents.
Section 2 CPU No. Addressing Mode and Instruction Format 5 Absolute address Effective Address Calculation Effective Address (EA) @aa:8 31 op abs @aa:16 31 op 0 H'FFFF 24 23 16 15 Sign extension 0 24 23 0 Don’t care abs @aa:24 31 op 87 24 23 Don’t care Don’t care abs @aa:32 op 31 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 24 23 0 Don’t care Operand is immediate data.
Section 2 CPU No. Addressing Mode and Instruction Format 8 Memory indirect @@aa:8 • Effective Address Calculation Effective Address (EA) Normal mode op abs 31 87 0 abs H'000000 31 24 23 Don’t care 16 15 0 H'00 0 15 Memory contents • Advanced mode op abs 31 87 H'000000 31 abs 0 Memory contents Rev. 4.
Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Section 2 CPU End of bus request Bus request Program execution state End of bus request SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1.
Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority.
Section 2 CPU Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.
Section 2 CPU 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU and other bus masters operate on a medium-speed clock.
Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state.
Section 2 CPU Bus cycle T1 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.18 Pin States during On-Chip Memory Access Rev. 4.
Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. Rev. 4.
Section 2 CPU 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection This LSI has three operating modes (modes 1 to 3). These modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and MD0). Table 3.1 lists the MCU operating modes. Table 3.
Section 3 MCU Operating Modes 3.1.2 Register Configuration This LSI have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1 and MD0), a system control register (SYSCR) and bus control register (BCR) that control the operation of the MCU, and a serial/timer control register (STCR) that controls the operation of the supporting modules. Table 3.2 summarizes these registers. Table 3.
Section 3 MCU Operating Modes Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and written. Bit 7 EXPE Description 0 Single chip mode is selected 1 Expanded mode is selected Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Section 3 MCU Operating Modes Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode.
Section 3 MCU Operating Modes Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled 3.2.
Section 3 MCU Operating Modes 3.2.4 Serial Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions), and also selects the TCNT input clock.
Section 3 MCU Operating Modes Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control register (PCSR and SYSCR2).
Section 3 MCU Operating Modes 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1.
Section 3 MCU Operating Modes 3.5 Memory Map in Each Operating Mode Figures 3.1 to 3.5 show memory maps for each of the operating modes. The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2 (advanced mode). The on-chip ROM capacity is 64 kbytes (H8S/2142, H8S/2147, and H8S/2147N), 96 kbytes (H8S/2143), or 128 kbytes (H8S/2144 and H8S/2148), but only 56 kbytes are available in mode 3 (normal mode).
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 On-chip RAM* On-chip RAM* H'EFFF H'E080 H'EFFF H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O register
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM H'01FFFF H'020000 On-chip ROM H'01FFFF External address space H'FFE080 H'FFE080 On-chip RAM* On-chip RAM H'FFEFFF H'FFEFFF External address space H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)* H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 On-chip RAM* H'EFFF H'E080 On-chip RAM* External address space H'F800 Reserved area H'FE4F H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM H'01FFFF H'020000 On-chip ROM H'01FFFF External address space H'FFE080 H'FFE080 On-chip RAM* H'FFEFFF External address space H'FFF800 Reserved area H'FFFE4F H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)* H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF On-chip RAM H'FFEFFF H'FFFE50 H'FFFEFF H'FFF
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 H'E080 On-chip RAM* On-chip RAM* H'EFFF H'EFFF H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O register
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM H'017FFF On-chip ROM H'017FFF Reserved area H'01FFFF H'020000 Reserved area H'01FFFF External address space H'FFE080 H'FFE080 On-chip RAM* On-chip RAM H'FFEFFF H'FFEFFF External address space H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)* H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFFE
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'DFFF H'DFFF External address space H'E080 H'E880 H'EFFF H'E080 H'E080 Reserved area* Reserved area* On-chip RAM* H'E880 H'EFFF External address space H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'F
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF Reserved area H'01FFFF H'020000 Reserved area H'01FFFF External address space H'FFE080 H'FFE080 Reserved area* H'FFE880 H'FFEFFF On-chip RAM* Reserved area H'FFE880 H'FFEFFF On-chip RAM External address space H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)* H'FFFF7F
Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM On-chip ROM External address space H'DFFF H'DFFF External address space H'E080 H'E880 H'EFFF Reserved area* On-chip RAM* H'E080 H'E880 H'EFFF External address space H'F800 Reserved area H'FE4F H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H
Section 3 MCU Operating Modes Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF Reserved area H'01FFFF H'020000 H'01FFFF External address space H'FFE080 Reserved area* H'FFE880 H'FFEFFF Reserved area On-chip RAM* H'FFE080 Reserved area H'FFE880 H'FFEFFF On-chip RAM External address space H'FFF800 Reserved area H'FFFE4F H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM
Section 3 MCU Operating Modes Rev. 4.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state.
Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The MCUs can also be reset by overflow of the watchdog timer.
Section 4 Exception Handling Fetch of Vector Internal first program fetch processing instruction φ RES Internal address bus (1) (3) Internal read signal Internal write signal High Internal data bus (2) (1) (2) (3) (4) (4) Reset exception vector address ((1) = H'0000) Start address (contents of reset exception vector address) Start address ((3) = (2)) First program instruction Figure 4.2 Reset Sequence (Mode 3) Rev. 4.
Section 4 Exception Handling Vector fetch φ Internal processing Fetch of first program instruction * * * (1) (3) (5) RES Address bus RD High HWR, LWR (2) D15 to D8 (1) (3) (2) (4) (5) (6) (4) (6) Reset exception vector address ((1) = H'0000, (3) = H'0001) Start address (contents of reset exception vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 1) 4.2.
Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0) from 23 input pins (NMI, IRQ7 to IRQ0, and KIN15 to KIN0), and internal sources in the on-chip supporting modules. Figure 4.4 shows the interrupt sources and the number of interrupts of each type.
Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.
Section 4 Exception Handling 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode) SP CCR PC (24 bits) Interrupt control modes 0 and 1 Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode) Rev. 4.
Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features This LSI control interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities.
Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1.
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected.
Section 5 Interrupt Controller 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.
Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI, among other functions. Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.
Section 5 Interrupt Controller 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC) Bit 7 6 5 4 3 2 1 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI and address break. The correspondence between ICR settings and interrupt sources is shown in table 5.3.
Section 5 Interrupt Controller 5.2.3 IRQ Enable Register (IER) Bit 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode.
Section 5 Interrupt Controller ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.
Section 5 Interrupt Controller Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests.
Section 5 Interrupt Controller 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) 7 Bit 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins KIN7 to KIN0).
Section 5 Interrupt Controller Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control key-sense input interrupt requests (KIN15 to KIN8). Bits 7 to 0 KMIMR15 to KMIMR8 Description 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled (Initial value) Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, and registers KMIMR and KMIMRA.
Section 5 Interrupt Controller If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). 5.2.
Section 5 Interrupt Controller 5.2.
Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts. 5.3.1 External Interrupts There are nine external interrupt sources from 25 input pins (23 actual pins): NMI, IRQ7 to IRQ0, and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source.
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S Q IRQn interrupt request R IRQn input Clear signal Note: n: 7 to 0 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.4 shows the timing of IRQnF setting. φ IRQn input pin IRQnF Figure 5.4 Timing of IRQnF Setting The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Section 5 Interrupt Controller Interrupts KIN15 to KIN0 Interrupts KIN15 to KIN0 are requested by input signals at pins KIN15 to KIN 0. When any of pins KIN15 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should be cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN15 to KIN8 correspond to the IRQ7 interrupt, and interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Vector Address Origin of Interrupt Source Vector Normal Number Mode 8-bit timer channel 0 64 65 OVI0 (overflow) 66 H'0084 H'000108 Reserved 67 H'0086 H'00010C 68 H'0088 H'000110 69 H'008A H'000114 OVI1 (overflow) 70 H'008C H'000118 Reserved 71 H'008E H'00011C 72 H'0090 H'000120 Interrupt Source CMIA0 (compare-match A) CMIB0 (compare-match B) CMIA1 (compare-match A) CMIB1 (compare-match B) CMIAY (compare-match A) CMIBY (compare-match B) 8-bit ti
Section 5 Interrupt Controller Vector Address Interrupt Source Origin of Interrupt Source IICI1 (1-byte transmission/ reception completed) IIC channel 1 94 (option) Reserved PS2IA (reception completed A) PS2IB (reception completed B) PS2IC (reception completed C) Keyboard buffer controller (PS2) Reserved Reserved — Vector Normal Number Mode Advanced Mode ICR H'00BC H'000178 ICRC3 High 95 H'00BE H'00017C 96 H'00C0 H'000180 97 H'00C2 H'000184 98 H'00C4 H'000188 99 H'00C6 H'00018C
Section 5 Interrupt Controller 5.4 Address Breaks 5.4.1 Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.4.
Section 5 Interrupt Controller 5.4.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction.
Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Vector fetch Stack save Internal Instruction operation fetch φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 Interrupt exception handling NOP NOP NOP execution execution execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP
Section 5 Interrupt Controller 5.5 Interrupt Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI and address break interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Section 5 Interrupt Controller Figure 5.7 shows a block diagram of the priority decision circuit. I UI ICR Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case. 1.
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes No No IRQ0? Yes IRQ0? No Yes IRQ1? Yes No IRQ1? Yes PS2IC? PS2IC? Yes Yes No I = 0? Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 4.
Section 5 Interrupt Controller 5.5.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. • Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1.
Section 5 Interrupt Controller Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending.
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes IRQ0? Yes No No IRQ0? No Yes IRQ1? No IRQ1? Yes Yes PS2IC? PS2IC? Yes Yes No I = 0? Yes UI = 0? I=0 No No Yes Yes Save PC and CCR I ← 1, UI ← 1 Read vector address Branch to interrupt handling routine Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 4.
Section 5 Interrupt Controller 5.5.4 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 4.
Rev. 4.00 Sep 27, 2006 page 144 of 1130 REJ09B0327-0400 Figure 5.11 Interrupt Exception Handling (1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.5.5 Interrupt Response Times This LSI are capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM. Table 5.8 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 5.8 are explained in table 5.9. Table 5.
Section 5 Interrupt Controller 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.6.2 Instructions That Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed.
Section 5 Interrupt Controller 5.7 DTC Activation by Interrupt 5.7.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). 5.7.2 Block Diagram Figure 5.13 shows a block diagram of the DTC and interrupt controller.
Section 5 Interrupt Controller 5.7.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
Section 5 Interrupt Controller Usage Note SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. Rev. 4.
Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview This LSI have a built-in bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states, to be set. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below.
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. External bus control signals Internal control signals Bus controller Bus mode signal WSCR BCR WAIT Internal data bus Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev. 4.
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.
Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Control Register (BCR) Bit 7 6 5 4 3 2 1 0 ICIS1 ICIS0 — IOS1 IOS0 Initial value 1 1 0 1 0 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of the I/O area when the I/O strobe function has been selected for the AS pin.
Section 6 Bus Controller Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max.
Section 6 Bus Controller Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits. Always write 0 when writing to these bits in the A-mask version. Bit 5—Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access space or 16-bit access space.
Section 6 Bus Controller Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait states when external memory space is accessed while the AST bit is set to 1. Bit 1 Bit 0 WC1 WC0 Description 0 0 No program wait states are inserted 1 1 program wait state is inserted in external memory space accesses 0 2 program wait states are inserted in external memory space accesses 1 3 program wait states are inserted in external memory space accesses (Initial value) 1 6.
Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) ABW AST WMS1 WMS0 WC1 WC0 Bus Width Access States Program Wait States 0 0 — — — — 16 2 0 1 0 1 — — 16 3 0 —* —* 0 0 3 0 1 1 0 — — 1 0 1 —* —* — 6.3.
Section 6 Bus Controller 6.3.4 I/O Select Signal In this LSI, an I/O select signal (IOS) can be output, with the signal output going low when the designated external space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 φ Address bus External address in IOS set range IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR.
Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with the ABW bit, the AST bit, and the WMS1, WMS0, WC1, and WC0 bits (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller 16-Bit Access Space Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd.
Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.5 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space Figure 6.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit 2-State Access Space Rev. 4.
Section 6 Bus Controller 8-Bit 3-State Access Space Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit 3-State Access Space Rev. 4.
Section 6 Bus Controller 16-Bit, 2-State Access Space Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access space. When 16-bit access space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid Undefined Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR HIgh LWR Write D15 to D8 D7 to D0 Undefined Valid Figure 6.8 16-Bit, 2-State Access Space Bus Timing (2) (Odd Address Byte Access) Rev. 4.
Section 6 Bus Controller Bus cycle T2 T1 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.9 16-Bit, 2-State Access Space Bus Timing (3) (Word Access) Rev. 4.
Section 6 Bus Controller 16-Bit, 3-State Access Space Figures 6.10 to 6.12 show the bus timing for 16-bit, 3-state access space. When 16-bit access space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 Valid D7 to D0 Undefined Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.11 16-Bit, 3-State Access Space Bus Timing (2) (Odd Address Byte Access) Rev. 4.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.12 16-Bit, 3-State Access Space Bus Timing (3) (Word Access) Rev. 4.
Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the MCU can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion using the WAIT pin, and a combination of the two. Program Wait Mode: In program wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T2 and T3 states when external space is accessed.
Section 6 Bus Controller By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling using the φ clock. Figure 6.13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input disabled. Rev. 4.
Section 6 Bus Controller 6.5 Burst ROM Interface 6.5.1 Overview With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. External space can be designated as burst ROM space by means of the BRSTRM bit in BCR. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.
Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 (a) Example of Burst ROM Access Timing (when AST = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 φ Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 (b) Example of Burst ROM Access Timing (when AST = BRSTS1 = 0) Rev. 4.
Section 6 Bus Controller 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 6.6 Idle Cycle 6.6.1 Operation When this LSI chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle.
Section 6 Bus Controller Bus cycle A T1 T2 Bus cycle A Bus cycle B T3 T1 T2 T1 φ φ Address bus Address bus RD RD HWR, LWR HWR, LWR Data bus Data bus Long output floating time T2 Pin States in Idle Cycle Table 6.6 shows pin states in an idle cycle. Pin States in Idle Cycle Pins Pin State A23 to A0, IOS Contents of next bus cycle D15 to D0 High impedance AS High RD High HWR, LWR High Rev. 4.
Section 6 Bus Controller 6.7 Bus Arbitration 6.7.1 Overview This LSI have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and the DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 6 Bus Controller 6.7.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC.
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N. 7.1 Overview The H8S/2148 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.
Section 7 Data Transfer Controller (DTC) 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Section 7 Data Transfer Controller (DTC) 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.
Section 7 Data Transfer Controller (DTC) 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) 7 Bit Initial value Read/Write 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRA is an 8-bit register that controls the DTC operating mode.
Section 7 Data Transfer Controller (DTC) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 MD1 MD0 Description 0 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — 1 Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer, multiple data transfers can be performed consecutively in response to a single transfer request.
Section 7 Data Transfer Controller (DTC) 7.2.3 DTC Source Address Register (SAR) 23 Bit Initial value Read/write 22 21 20 19 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — 4 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.
Section 7 Data Transfer Controller (DTC) 7.2.5 DTC Transfer Count Register A (CRA) 15 Bit Initial value Read/Write 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) Bit 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources.
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) 7 Bit 6 5 4 3 2 0 1 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
Section 7 Data Transfer Controller (DTC) 7.2.9 Module Stop Control Register (MSTPCR) MSTPCRH 7 Bit 6 5 4 3 MSTPCRL 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Initial value Read/Write 0 0 1 1 1 1 1 1 7 6 5 4 3 2 1 0 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
Section 7 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No Transfer counter = 0 or DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 7.2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
Section 7 Data Transfer Controller (DTC) Table 7.
Section 7 Data Transfer Controller (DTC) The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0. Table 7.
Section 7 Data Transfer Controller (DTC) 7.3.3 DTC Vector Table Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
Section 7 Data Transfer Controller (DTC) Table 7.
Section 7 Data Transfer Controller (DTC) 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (vector address contents). In chain transfer, locate the register information in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
Section 7 Data Transfer Controller (DTC) 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.
Section 7 Data Transfer Controller (DTC) 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial address register state specified by the transfer counter and repeat area resumes and transfer is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.
Section 7 Data Transfer Controller (DTC) 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is specified as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified in the block area is restored. The other address register is successively incremented or decremented, or left fixed.
Section 7 Data Transfer Controller (DTC) First block SAR or DAR · · · Block area DAR or SAR Transfer Nth block Figure 7.8 Memory Mapping in Block Transfer Mode Rev. 4.
Section 7 Data Transfer Controller (DTC) 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows memory mapping for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 7.
Section 7 Data Transfer Controller (DTC) 7.3.9 Operation Timing Figures 7.10 to 7.12 show examples of DTC operation timing. φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.
Section 7 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.
Section 7 Data Transfer Controller (DTC) Table 7.
Section 7 Data Transfer Controller (DTC) 7.3.11 Procedures for Using the DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 7 Data Transfer Controller (DTC) 7.3.12 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 7 Data Transfer Controller (DTC) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Section 7 Data Transfer Controller (DTC) 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Section 7 Data Transfer Controller (DTC) Rev. 4.
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview This LSI have ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7). Tables 8.1 to 8.3 summarize the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, A, and B have a built-in MOS input pull-up function.
Section 8 I/O Ports Table 8.
Section 8 I/O Ports Expanded Modes Port Port 4 Description Pins • 8-bit I/O port P47/PWX1 P46/PWX0 P45/TMRI1/ HIRQ12/CSYNCI P44/TMO1/ HIRQ1/HSYNCO P43/TMCI1/ HIRQ11/HSYNCI P42/TMRI0/ SCK2/SDA1 P41/TMO0/ RxD2/IrRxD P40/TMCI0/ TxD2/IrTxD Port 5 • 3-bit I/O port P52/SCK0/SCL0 P51/RxD0 Mode 1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection input/output (HSYNCO, CSYNCI,
Section 8 I/O Ports Expanded Modes Port Port 7 Description Pins • 8-bit I/O port P77/AN7/DA1 P76/AN6/DA0 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) Input port also functioning as A/D converter analog input (AN7 to AN0) and D/A converter analog output (DA1, DA0) P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 8 • 7-bit I/O port P86/IRQ5/SCK1/ SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 I/O port also functioning as external interrupt input (IRQ5, IRQ4, IRQ3), SCI1 input/ou
Section 8 I/O Ports Expanded Modes Port Port 9 Description Pins • 8-bit I/O port P92/IRQ0 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as external interrupt input (IRQ0, IRQ1) P91/IRQ1 P90/LWR/IRQ2/ ADTRG/ECS2 Port A • 8-bit I/O port PA7/A23/KIN15/ CIN15/PS2CD PA6/A22/KIN14/ CIN14/PS2CC PA5/A21/KIN13/ CIN13/PS2BD PA4/A20/KIN12/ CIN12/PS2BC PA3/A19/KIN11/ CIN11/PS2AD PA2/A18/KIN10/ CIN10/PS2AC PA1/A17/KIN9/ CIN9 PA0/A16/KIN8/ CIN8 Port B •
Section 8 I/O Ports Table 8.
Section 8 I/O Ports Expanded Modes Port Port 5 Description Pins • 3-bit I/O port P52/SCK0/SCL0 P51/RxD0 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as SCI0 input/output (TxD0, RxD0, SCK0) and I2C bus interface 0 (option) input/output (SCL0) P50/TxD0 Port 6 • 8-bit I/O port P67/IRQ7/KIN7/ CIN7 P66/IRQ6/FTOB/ KIN6/CIN6 I/O port also functioning as external interrupt input (IRQ7, IRQ6), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTO
Section 8 I/O Ports Expanded Modes Port Port 9 Description Pins • 8-bit I/O port P97/WAIT/SDA0 Mode 1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as expanded data bus control input (WAIT) and I2C bus interface 0 (option) input/output (SDA0) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as I2C bus interface 0 (option) input/output (SDA0) P96/φ/EXCL When DDR = When DDR = 0 (after reset): input port or EXCL 0: input port or input EXCL input When DDR = 1: φ output When DD
Section 8 I/O Ports Expanded Modes Port Port B Description Pins • 8-bit I/O port PB7/D7 PB6/D6 PB5/D5 Mode 1 Mode 2, Mode 3 (EXPE = 1) In 8-bit bus mode (ABW = 1): I/O port In 16-bit bus mode (ABW = 0): data bus input/output (D7 to D0) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as HIF control input/output pins (CS3, CS4, HIRQ3, HIRQ4) PB4/D4 PB3/D3/CS4 PB2/D2/CS3 PB1/D1/HIRQ4 PB0/D0/HIRQ3 Rev. 4.
Section 8 I/O Ports Table 8.
Section 8 I/O Ports Expanded Modes Port Port 6 Description Pins • 8-bit I/O port P67/IRQ7/KIN7/ CIN7 P66/IRQ6/FTOB/ KIN6/CIN6 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as external interrupt input (IRQ7, IRQ6), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to KIN0), and expansion A/D converter input (CIN7 to CIN0) P65/FTID/KIN5/ CIN5 P64/FTIC/KIN4/ CIN4 P63/FTIB/KIN3/
Section 8 I/O Ports Expanded Modes Port Port 9 Description Pins • 8-bit I/O port P97/WAIT Mode 1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as expanded data bus control input (WAIT) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port P96/φ/EXCL When DDR = When DDR = 0 (after reset): input port or EXCL 0: input port or input EXCL input When DDR = 1: φ output When DDR = 1 (after reset): φ output P95/AS/IOS Expanded data bus control output(AS/IOS, HWR, RD) P94/HWR I/O port P93/RD P92/IRQ
Section 8 I/O Ports 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus output pins (A7 to A0), and as 8-bit PWM output pins (PW7 to PW0) (H8S/2148 Group and H8S/2147N only). Port 1 functions change according to the operating mode. Port 1 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.1 shows the port 1 pin configuration.
Section 8 I/O Ports 8.2.2 Register Configuration Table 8.4 shows the port 1 register configuration. Table 8.4 Port 1 Registers Name Abbreviation R/W Initial Value Address* Port 1 data direction register P1DDR W H'00 H'FFB0 Port 1 data register P1DR R/W H'00 H'FFB2 Port 1 MOS pull-up control register P1PCR R/W H'00 H'FFAC Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port 1 Data Register (P1DR) Bit Initial value R/W 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read directly, regardless of the actual pin states.
Section 8 I/O Ports 8.2.3 Pin Functions in Each Mode Mode 1 In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are shown in figure 8.2. A7 (Output) A6 (Output) A5 (Output) Port 1 A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) Figure 8.
Section 8 I/O Ports Port 1 When P1DDR = 1 and PWOERA = 0 When P1DDR = 0 When P1DDR = 1 and PWOERA = 1 A7 (Output) P17 (Input) PW7 (Output) A6 (Output) P16 (Input) PW6 (Output) A5 (Output) P15 (Input) PW5 (Output) A4 (Output) P14 (Input) PW4 (Output) A3 (Output) P13 (Input) PW3 (Output) A2 (Output) P12 (Input) PW2 (Output) A1 (Output) P11 (Input) PW1 (Output) A0 (Output) P10 (Input) PW0 (Output) Figure 8.
Section 8 I/O Ports 8.2.4 MOS Input Pull-Up Function Port 1 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode.
Section 8 I/O Ports Port 2 Port 2 pins Pin functions in mode 1 P27/A15/PW15/CBLANK A15 (Output) P26/A14/PW14 A14 (Output) P25/A13/PW13 A13 (Output) P24/A12/PW12 A12 (Output) P23/A11/PW11 A11 (Output) P22/A10/PW10 A10 (Output) P21/A9/PW9 A9 (Output) P20/A8/PW8 A8 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output) A14 (Output)/P26 (I/O)/PW14 (Output) A13 (Output)/P25 (I/O)/PW13 (Output) A12 (Output)/P24 (I/O)/PW12 (Output) A11 (Output)/P2
Section 8 I/O Ports 8.3.2 Register Configuration Table 8.6 shows the port 2 register configuration. Table 8.6 Port 2 Registers Name Abbreviation R/W Initial Value Address* Port 2 data direction register P2DDR W H'00 H'FFB1 Port 2 data register P2DR R/W H'00 H'FFB3 Port 2 MOS pull-up control register P2PCR R/W H'00 H'FFAD Note: * Lower 16 bits of the address.
Section 8 I/O Ports • Modes 2 and 3 (EXPE = 0) The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting.
Section 8 I/O Ports 8.3.3 Pin Functions in Each Mode Mode 1 In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are shown in figure 8.6. A15 (Output) A14 (Output) A13 (Output) Port 2 A12 (Output) A11 (Output) A10 (Output) A9 (Output) A8 (Output) Figure 8.
Section 8 I/O Ports When P2DDR = 1 and PWOERB = 0 When P2DDR = 0 When P2DDR = 1 and PWOERB = 1 A15 (Output)/P27 (Output) P27 (Input)/CBLANK (Output) PW15 (Output)/CBLANK (Output) Port 2 A14 (Output)/P26 (Output) P26 (Input) PW14 (Output) A13 (Output)/P25 (Output) P25 (Input) PW13 (Output) A12 (Output)/P24 (Output) P24 (Input) PW12 (Output) A11 (Output) P23 (Input) PW11 (Output) A10 (Output) P22 (Input) PW10 (Output) A9 (Output) P21 (Input) PW9 (Output) A8 (Output) P20 (Input) PW8 (Out
Section 8 I/O Ports 8.3.4 MOS Input Pull-Up Function Port 2 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode.
Section 8 I/O Ports 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port. Port 3 pins also function as host data bus I/O pins (HDB7 to HDB0) (H8S/2148 Group and H8S/2147N only), and as data bus I/O pins. Port 3 functions change according to the operating mode. Port 3 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.9 shows the port 3 pin configuration.
Section 8 I/O Ports 8.4.2 Register Configuration Table 8.8 shows the port 3 register configuration. Table 8.8 Port 3 Registers Name Abbreviation R/W Initial Value Address* Port 3 data direction register P3DDR W H'00 H'FFB4 Port 3 data register P3DR R/W H'00 H'FFB6 Port 3 MOS pull-up control register P3PCR R/W H'00 H'FFAE Note: * Lower 16 bits of the address.
Section 8 I/O Ports Port 3 Data Register (P3DR) 7 6 5 4 3 2 1 0 P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30). If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states.
Section 8 I/O Ports 8.4.3 Pin Functions in Each Mode Modes 1, 2, and 3 (EXPE = 1) In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. The port 3 pin functions are shown in figure 8.10. D15 (I/O) D14 (I/O) D13 (I/O) Port 3 D12 (I/O) D11(I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 8.
Section 8 I/O Ports P37 (I/O)/HDB7 (I/O) P36 (I/O)/HDB6 (I/O) P35 (I/O)/HDB5 (I/O) P34 (I/O)/HDB4 (I/O) Port 3 P33 (I/O)/HDB3 (I/O) P32 (I/O)/HDB2 (I/O) P31 (I/O)/HDB1 (I/O) P30 (I/O)/HDB0 (I/O) Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0)) 8.4.4 MOS Input Pull-Up Function Port 3 has a built-in MOS input pull-up function that can be controlled by software.
Section 8 I/O Ports 8.5 Port 4 8.5.1 Overview Port 4 is an 8-bit I/O port.
Section 8 I/O Ports Port 4 Data Direction Register (P4DDR) Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned.
Section 8 I/O Ports (IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin (SDA1). The port 4 pin functions are shown in table 8.11. Table 8.11 Port 4 Pin Functions Pin Selection Method and Pin Functions P47/PWX1 The pin function is switched as shown below according to the combination of bit OEB in DACR of 14-bit PWM, and bit P47DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P43/TMCI1/ HIRQ11/HSYNCI The pin function is switched as shown below according to the combination of the operating mode and bit P43DDR. P43DDR 0 Operating mode — Not slave mode Slave mode P43 input pin P43 output pin HIRQ11 output pin Pin function 1 TMCI1 input pin, HSYNCI input pin When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1, this pin is used as the TMCI1 input pin.
Section 8 I/O Ports Pin Selection Method and Pin Functions P41/TMO0/RxD2/ The pin function is switched as shown below according to the combination of IrRxD bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR. OS3 to OS0 All 0 RE P41DDR Pin function Not all 0 0 1 0 0 1 — — P41 input pin P41 output pin RxD2/IrRxD input pin TMO0 output pin When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be cleared to 0.
Section 8 I/O Ports 8.6 Port 5 8.6.1 Overview Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the IIC0 I/O pin (SCL0) (option in H8S/2148 Group and H8S/2147N only). In the H8S/2148 Group and H8S/2147N, P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 pin functions are the same in all operating modes. Figure 8.13 shows the port 5 pin configuration.
Section 8 I/O Ports Port 5 Data Direction Register (P5DDR) 7 6 5 4 3 — — — — — Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W Bit 2 1 0 P52DDR P51DDR P50DDR P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are reserved.
Section 8 I/O Ports 8.6.3 Pin Functions Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The port 5 pin functions are shown in table 8.13. Table 8.13 Port 5 Pin Functions Pin Selection Method and Pin Functions P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI0, bit C/A in SMR of SCI0, bit ICE in ICCR of IIC0, and bit P52DDR.
Section 8 I/O Ports 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port.
Section 8 I/O Ports 8.7.2 Register Configuration Table 8.14 shows the port 6 register configuration. Table 8.14 Port 6 Registers Name Abbreviation R/W Initial Value 1 Address* Port 6 data direction register P6DDR W H'00 H'FFB9 Port 6 data register P6DR R/W H'00 Port 6 MOS pull-up control register KMPCR R/W H'00 H'FFBB 2 H'FFF2* System control register 2 SYSCR2 R/W H'00 H'FF83 Notes: 1. Lower 16 bits of the address. 2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY.
Section 8 I/O Ports Port 6 Data Register (P6DR) 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states.
Section 8 I/O Ports System Control Register 2 (SYSCR2) (H8S/2148 Group and H8S/2147N Only) Bit 7 6 KWUL1 KWUL0 5 4 3 2 1 0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the operation of host interface functions. Only bits 7, 6, and 5 are described here. See section 18.2.
Section 8 I/O Ports 8.7.3 Pin Functions Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense interrupt input pins (KIN7 to KIN0), comparator input pins (CIN7 to CIN0), and external interrupt input pins (IRQ7, IRQ6).
Section 8 I/O Ports Pin Selection Method and Pin Functions P64/FTIC/KIN4/ CIN4/CLAMPO The pin function is switched as shown below according to the combination of bit CLOE in TCONRO of the timer connection function and bit P64DDR. CLOE 0 P64DDR Pin function 1 0 1 — P64 input pin P64 output pin CLAMPO output pin FTIC input pin, KIN4 input pin, CIN4 input pin This pin can always be used as the FTIC, KIN4, or CIN4 input pin.
Section 8 I/O Ports Pin Selection Method and Pin Functions P60/FTCI/TMIX/ KIN0/CIN0/ HFBACKI P60DDR Pin function 0 1 P60 input pin P60 output pin FTCI input pin, HFBACKI input pin, TMIX input pin, KIN0 input pin, CIN0 input pin This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin. 8.7.
Section 8 I/O Ports 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all operating modes. Figure 8.15 shows the port 7 pin configuration.
Section 8 I/O Ports Port 7 Input Data Register (P7PIN) 7 Bit 6 P77PIN P76PIN 5 P75PIN 4 3 2 P74PIN P73PIN P72PIN 1 0 P71PIN P70PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins P77 to P70. When a P7PIN read is performed, the pin states are always read. P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR and the port B setting will be changed. 8.8.
Section 8 I/O Ports 8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1) (option in H8S/2148 Group and H8S/2147N only), HIF I/O pins (CS2, GA20, HA0, HIFSD) (H8S/2148 Group and H8S/2147N only), and external interrupt input pins (IRQ5 to IRQ3). Port 8 pin functions are the same in all operating modes. Figure 8.16 shows the port 8 pin configuration.
Section 8 I/O Ports Port 8 Data Direction Register (P8DDR) Bit 7 — 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port 8. P8DDR has the same address as PBPIN, and if read, the port B state will be returned.
Section 8 I/O Ports Table 8.19 Port 8 Pin Functions Pin Selection Method and Pin Functions P86/IRQ5/SCK1/ SCL1 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI1, bit C/A in SMR of SCI1, bit ICE in ICCR of IIC1, and bit P86DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P83 The pin function is switched as shown below according to bit P83DDR. P83DDR Pin function P82/HIFSD 0 1 P83 input pin P83 output pin The pin function is switched as shown below according to the combination of operating mode, bit SDE in SYSCR2, and bit P82DDR.
Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter external trigger input pin (ADTRG), host interface input pins (ECS2, CS1, IOW, IOR) (H8S/2148 Group and H8S/2147N only), the IIC0 I/O pin (SDA0) (option in H8S/2148 Group and H8S/2147N only), the subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, HWR, LWR, WAIT), and the system clock (φ) output pin.
Section 8 I/O Ports 8.10.2 Register Configuration Table 8.20 summarizes the port 9 registers. Table 8.20 Port 9 Registers Name Abbreviation R/W Initial Value 1 Address* Port 9 data direction register P9DDR W H'40/H'00* H'FFC0 Port 9 data register P9DR R/W H'00 2 H'FFC1 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
Section 8 I/O Ports When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR), regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90 becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0. • Modes 2 and 3 (EXPE = 0) When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and pins P97 and P95 to P90 become output ports.
Section 8 I/O Ports Table 8.21 Port 9 Pin Functions Pin Selection Method and Pin Functions P97/WAIT/SDA0 The pin function is switched as shown below according to the combination of operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P94/HWR/IOW The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P94DDR. Operating mode — P94DDR — 0 1 — HWR output pin P94 input pin P94 output pin IOW input pin 0 1 The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P93DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions P90/LWR/IRQ2/ ADTRG/ECS2 The pin function is switched as shown below according to the combination of operating mode, bit ABW in WSCR, bits HI12E and CS2E in SYSCR2, bit FGA20E in HICR, and bit P90DDR.
Section 8 I/O Ports 8.11 Port A 8.11.1 Overview Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins (PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD) (H8S/2148 Group and H8S/2147N only), key-sense interrupt input pins (KIN15 to KIN8), expansion A/D converter input pins (CIN15 to CIN8), and address output pins (A23 to A16). Port A pin functions are the same in all operating modes. Figure 8.18 shows the port A pin configuration.
Section 8 I/O Ports 8.11.2 Register Configuration Table 8.22 summarizes the port A registers. Table 8.22 Port A Registers Name Abbreviation R/W Initial Value 1 Address* Port A data direction register PADDR W H'00 2 H'FFAB* Port A output data register PAODR R/W H'00 H'FFAA Port A input data register PAPIN R Undefined 2 H'FFAB* Notes: 1. Lower 16 bits of the address. 2. PADDR and PAPIN have the same address.
Section 8 I/O Ports PAODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port A Input Data Register (PAPIN) Bit 7 6 5 4 3 2 1 0 PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PA7 to PA0. Reading PAPIN always returns the pin states. 8.11.
Section 8 I/O Ports Pin Selection Method and Pin Functions PA6/A22/PS2CC/ KIN14/CIN14 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA6DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PA4/A20/PS2BC/ KIN12/CIN12 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA4DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PA2/A18/PS2AC/ KIN10/CIN10 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA2DDR.
Section 8 I/O Ports 8.11.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAODR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up for pins PA7 to PA4 is always off when IICS is set to 1.
Section 8 I/O Ports 8.12 Port B 8.12.1 Overview Port B is an 8-bit I/O port. Port B pins also have HIF input/output pins (CS3, CS4, HIRQ3, HIRQ4) (H8S/2148 Group and H8S/2147N only), and a data bus input/output function (as D7 to D0). The pin functions depend on the operating mode. Figure 8.19 shows the port B pin configuration.
Section 8 I/O Ports 8.12.2 Register Configuration Table 8.25 summarizes the port B registers. Table 8.25 Port B Registers Name Abbreviation R/W Initial Value 1 Address* Port B data direction register PBDDR W H'00 2 H'FFBE* Port B output data register PBODR R/W H'00 Port B input data register PBPIN R Undefined H'FFBC 3 H'FFBD* Notes: 1. Lower 16 bits of the address. 2. PBDDR has the same address as P7PIN. 3. PBPIN has the same address as P8DDR.
Section 8 I/O Ports • Modes 2 and 3 (EXPE = 0) A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. Port B Output Data Register (PBODR) Bit 7 6 5 4 3 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PBODR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0).
Section 8 I/O Ports 8.12.3 Pin Functions Port B pins also function as HIF input pins (CS3, CS4, HIRQ3, HIRQ4) [H8S/2148 Group and H8S/2147N only] and data bus I/O pins (D7 to D0). The port B pin functions are shown in table 8.26. Table 8.26 Port B Pin Functions Pin Selection Method and Pin Functions PB7/D7 The pin function is switched as shown below according to the combination of the operating mode, bit PB7DDR, and bit ABW in WSCR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PB4/D4 The pin function is switched as shown below according to the combination of the operating mode, bit PB4DDR, and bit ABW in WSCR. Operating mode 0 PB4DDR — 0 1 0 1 D4 I/O pin PB4 input pin PB4 output pin PB4 input pin PB4 output pin 1 — The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and bit PB3DDR.
Section 8 I/O Ports Pin Selection Method and Pin Functions PB1/D1/HIRQ4 The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and bit PB1DDR.
Section 8 I/O Ports 8.12.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2 and 3 (EXPE = 1) with the ABW bit in WSCR set to 1, and in modes 2 and 3 (EXPE = 0), and can be specified as on or off on a bit-by-bit basis. When a PBDDR bit is cleared to 0, setting the corresponding PBODR bit to 1 turns on the MOS input pull-up for that pin.
Section 9 8-Bit PWM Timers Section 9 8-Bit PWM Timers Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N. 9.1 Overview The H8/2148 Group has an on-chip pulse width modulation (PWM) timer module with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division.
Section 9 8-Bit PWM Timers 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the PWM timer module.
Section 9 8-Bit PWM Timers 9.1.3 Pin Configuration Table 9.1 shows the PWM output pin. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output pin 0 to 15 PW0 to PW15 Output PWM timer pulse output 0 to 15 9.1.4 Register Configuration Table 9.2 lists the registers of the PWM timer module. Table 9.
Section 9 8-Bit PWM Timers 9.2 Register Descriptions 9.2.1 PWM Register Select (PWSL) Bit 7 6 PWCKE PWCKS 5 4 3 2 1 0 — — RS3 RS2 RS1 RS0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the PWM data register. PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode.
Section 9 8-Bit PWM Timers Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz Table 9.3 Internal Clock Frequency Resolution PWM Conversion Period Carrier Frequency φ 50 ns 12.8 µs 1250 kHz φ/2 100 ns 25.6 µs 625 kHz φ/4 200 ns 51.2 µs 312.5 kHz φ/8 400 ns 102.4 µs 156.3 kHz φ/16 800 ns 204.8 µs 78.1 kHz Bit 5—Reserved: This bit is always read as 1 and cannot be modified. Bit 4—Reserved: This bit is always read as 0 and cannot be modified.
Section 9 8-Bit PWM Timers 9.2.2 PWM Data Registers (PWDR0 to PWDR15) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period.
Section 9 8-Bit PWM Timers PWDPR is initialized to H'00 by a reset and in hardware standby mode. OS Description 0 PWM direct output (PWDR value corresponds to high width of output) 1 PWM inverted output (PWDR value corresponds to low width of output) 9.2.
Section 9 8-Bit PWM Timers 9.2.5 Peripheral Clock Select Register (PCSR) Bit 7 6 5 4 3 — — — — — 2 1 PWCKB PWCKA 0 — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — R/W R/W — PCSR is an 8-bit readable/writable register that selects the PWM timer input clock. PCSR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0.
Section 9 8-Bit PWM Timers 9.2.7 Port 2 Data Direction Register (P2DDR) Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port J on a bit-by-bit basis. Port 2 pins are multiplexed with pins PW8 to PW15. The bit corresponding to a pin to be used for PWM output should be set to 1.
Section 9 8-Bit PWM Timers 9.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
Section 9 8-Bit PWM Timers 9.3 Operation 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. Table 9.4 Upper 4 Bits 0000 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0001 0010 0011 0100 0101 0110 0111 .. . 1000 1001 1010 1011 1100 1101 1110 1111 Rev. 4.
Section 9 8-Bit PWM Timers The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 Position of Pulses Added to Basic Pulses Basic Pulse No.
Section 10 14-Bit PWM Timer (PWMX) Section 10 14-Bit PWM Timer (PWMX) 10.1 Overview This LSI have an on-chip 14-bit pulse-width modulator (PWM) with two output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR). 10.1.1 Features The features of the 14-bit PWM (D/A) are listed below. • The pulse is subdivided into multiple base cycles to reduce ripple.
Section 10 14-Bit PWM Timer (PWMX) 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM (D/A) module.
Section 10 14-Bit PWM Timer (PWMX) 10.1.3 Pin Configuration Table 10.1 lists the pins used by the PWM (D/A) module. Table 10.1 PWM Timer Input and Output Pins Name Abbr. I/O Function PWM output pin 0 PWX0 Output PWM output, channel A PWM output pin 1 PWX1 Output PWM output, channel B 10.1.4 Register Configuration Table 10.2 lists the registers of the PWM (D/A) module. Table 10.
Section 10 14-Bit PWM Timer (PWMX) 10.2 Register Descriptions 10.2.1 PWM (D/A) Counter (DACNT) DACNTH DACNTL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIT (Counter) 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — — REGS Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 — R/W DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse.
Section 10 14-Bit PWM Timer (PWMX) 10.2.
Section 10 14-Bit PWM Timer (PWMX) Bit 1—Carrier Frequency Select (CFS) Bit 1 CFS Description 0 Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD 1 Base cycle = resolution (T) × 256 DADR range = H'0103 to H'FFFF (Initial value) DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1. DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed.
Section 10 14-Bit PWM Timer (PWMX) Bit 7 TEST Description 0 PWM (D/A) in user state: normal operation 1 PWM (D/A) in test state: correct conversion results unobtainable (Initial value) Bit 6—PWM Enable (PWME): Starts or stops the PWM (D/A) counter (DACNT). Bit 6 PWME Description 0 DACNT operates as a 14-bit up-counter 1 DACNT halts at H'0003 (Initial value) Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1.
Section 10 14-Bit PWM Timer (PWMX) Bit 0—Clock Select (CKS): Selects the PWM (D/A) resolution. If the system clock (φ) frequency is 10 MHz, resolutions of 100 ns and 200 ns can be selected. Bit 0 CKS Description 0 Operates at resolution (T) = system clock cycle time (tcyc) 1 Operates at resolution (T) = system clock cycle time (tcyc) × 2 10.2.
Section 10 14-Bit PWM Timer (PWMX) 10.3 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written and read as follows (taking the example of the CPU interface). • Write When the upper byte is written, the upper-byte write data is stored in TEMP.
Section 10 14-Bit PWM Timer (PWMX) Table 10.3 Read and Write Access Methods for 16-Bit Registers Read Write Register Name Word Byte Word Byte DADRA and DADRB Yes Yes Yes × DACNT Yes × Yes × Legend: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). ×: This type of access may give incorrect results.
Section 10 14-Bit PWM Timer (PWMX) Upper-Byte Read CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'57) DACNTH (H'AA) DACNTL (H'57) Lower-Byte Read CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'57) DACNTH ( ) DACNTL ( ) Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) Rev. 4.
Section 10 14-Bit PWM Timer (PWMX) 10.4 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figure 10.4 shows the types of waveform output available.
Section 10 14-Bit PWM Timer (PWMX) Table 10.4 Settings and Operation (Examples when φ = 10 MHz) Resolution T CKS (µs) 0 0.1 CFS 0 1 1 0.2 0 1 Note: * Base Conversion Cycle Cycle (µs) (µs) 6.4 25.6 12.8 51.2 1638.4 1638.4 3276.8 3276.8 Fixed DADR Bits TL (if OS = 0) TH (if OS = 1) Bit Data Precision (Bits) 3 2 1 0 Conversion Cycle* (µs) 1. Always low (or high) level output (DADR = H'0001 to H'03FD) 14 1638.4 2. (Data value) × T (DADR = H'0401 to H'FFFD) 12 0 0 409.
Section 10 14-Bit PWM Timer (PWMX) 1. OS = 0 (DADR corresponds to TL) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL Figure 10.4 (1) Output Waveform b.
Section 10 14-Bit PWM Timer (PWMX) 2. OS = 1 (DADR corresponds to TH) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tH255 tf256 tH256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH Figure 10.4 (3) Output Waveform b.
Section 10 14-Bit PWM Timer (PWMX) Rev. 4.
Section 11 16-Bit Free-Running Timer Section 11 16-Bit Free-Running Timer 11.1 Overview This LSI have a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 Features The features of the free-running timer module are listed below.
Section 11 16-Bit Free-Running Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the free-running timer.
Section 11 16-Bit Free-Running Timer 11.1.3 Input and Output Pins Table 11.1 lists the input and output pins of the free-running timer module. Table 11.
Section 11 16-Bit Free-Running Timer 11.1.4 Register Configuration Table 11.2 lists the registers of the free-running timer module. Table 11.
Section 11 16-Bit Free-Running Timer 11.2 Register Descriptions 11.2.1 Free-Running Counter (FRC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by bits CKS1 and CKS0 in TCR.
Section 11 16-Bit Free-Running Timer 11.2.3 Input Capture Registers A to D (ICRA to ICRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four input capture registers, A to D, each of which is a 16-bit read-only register.
Section 11 16-Bit Free-Running Timer Table 11.3 Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Description 0 0 Captured on falling edge of input capture A (FTIA) 1 Captured on both rising and falling edges of input capture A (FTIA) 1 (Initial value) 0 1 Captured on rising edge of input capture A (FTIA) To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5φ).
Section 11 16-Bit Free-Running Timer 11.2.5 Output Compare Register DM (OCRDM) Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
Section 11 16-Bit Free-Running Timer Bit 7 ICIAE Description 0 Input capture interrupt request A (ICIA) is disabled 1 Input capture interrupt request A (ICIA) is enabled (Initial value) Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Section 11 16-Bit Free-Running Timer Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Section 11 16-Bit Free-Running Timer Bit 7 ICFA Description 0 [Clearing condition] (Initial value) Read ICFA when ICFA = 1, then write 0 in ICFA 1 [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal.
Section 11 16-Bit Free-Running Timer Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the signal transition in FTID (input capture signal) specified by the IEDGD bit, ICFD is set but data is not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt by setting the ICIDE bit to 1. ICFD must be cleared by software.
Section 11 16-Bit Free-Running Timer Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed (changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Section 11 16-Bit Free-Running Timer Bit 7 IEDGA Description 0 Capture on the falling edge of FTIA 1 Capture on the rising edge of FTIA (Initial value) Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B signal (FTIB). Bit 6 IEDGB Description 0 Capture on the falling edge of FTIB 1 Capture on the rising edge of FTIB (Initial value) Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C signal (FTIC).
Section 11 16-Bit Free-Running Timer Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for ICRB. Bit 2 BUFEB Description 0 ICRD is not used as a buffer register for input capture B 1 ICRD is used as a buffer register for input capture B (Initial value) Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal clock sources for the FRC.
Section 11 16-Bit Free-Running Timer Bit 7 ICRDMS Description 0 The normal operating mode is specified for ICRD 1 The operating mode using OCRDM is specified for ICRD (Initial value) Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF.
Section 11 16-Bit Free-Running Timer Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal (FTOA). Bit 3 OEA Description 0 Output compare A output is disabled 1 Output compare A output is enabled (Initial value) Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal (FTOB).
Section 11 16-Bit Free-Running Timer 11.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
Section 11 16-Bit Free-Running Timer 11.3 Operation 11.3.1 FRC Increment Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system clock (φ) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the increment timing. φ Internal clock FRC input clock FRC N–1 N N+1 Figure 11.
Section 11 16-Bit Free-Running Timer φ External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A.
Section 11 16-Bit Free-Running Timer 11.3.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. φ Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A 11.3.4 Input Capture Input Timing Input Capture Input Timing An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.
Section 11 16-Bit Free-Running Timer ICRA/B/C/D read cycle T1 T2 φ Input capture input pin Input capture signal Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D Is Read) Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 11.
Section 11 16-Bit Free-Running Timer When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however.
Section 11 16-Bit Free-Running Timer φ Input capture signal ICFA/B/C/D N FRC ICRA/B/C/D N Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D) 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value.
Section 11 16-Bit Free-Running Timer 11.3.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of this operation. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Setting of Overflow Flag (OVF) 11.3.
Section 11 16-Bit Free-Running Timer 11.3.9 ICRD and OCRDM Mask Signal Generation When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture function is generated. The mask signal is set by the input capture signal. The mask signal setting timing is shown in figure 11.15. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match.
Section 11 16-Bit Free-Running Timer 11.4 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.4 lists information about these interrupts. Table 11.
Section 11 16-Bit Free-Running Timer 11.5 Sample Application In the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: • The CCLRA bit in TCSR is set to 1. • Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.17 Pulse Output (Example) Rev. 4.
Section 11 16-Bit Free-Running Timer 11.6 Usage Notes Application programmers should note that the following types of contention can occur in the freerunning timer. Contention between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.18 shows this type of contention.
Section 11 16-Bit Free-Running Timer Contention between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.19 shows this type of contention. FRC write cycle T1 T2 φ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.
Section 11 16-Bit Free-Running Timer If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.21 shows this type of contention.
Section 11 16-Bit Free-Running Timer φ Address OCRAR(OCRAF) address Internal write signal OCRAR (OCRAF) Old data New data Compare-match signal Inhibited FRC N OCRA N N+1 The compare-match signal is inhibited and automatic addition does not occur. Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Not Used) Rev. 4.
Section 11 16-Bit Free-Running Timer Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 11.5. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ).
Section 11 16-Bit Free-Running Timer No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev. 4.
Section 12 8-Bit Timers Section 12 8-Bit Timers 12.1 Overview This LSI include an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-matches. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangularwave output with an arbitrary duty cycle.
Section 12 8-Bit Timers 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1). TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input capture function. For details, see section 13, Timer Connection.
Section 12 8-Bit Timers 12.1.3 Pin Configuration Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.
Section 12 8-Bit Timers 12.1.4 Register Configuration Table 12.2 summarizes the registers of the 8-bit timer module. Table 12.
Section 12 8-Bit Timers Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (Access is not divided into two 8-bit accesses.) In the H8S/2148 Group, certain of the channel X and channel Y registers are assigned to the same address. The TMRX/Y bit in TCONRS determines which register is accessed. 12.2 Register Descriptions 12.2.
Section 12 8-Bit Timers 12.2.2 Time Constant Register A (TCORA) TCORA0 TCORA1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORAX, TCORAY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORA is an 8-bit readable/writable register.
Section 12 8-Bit Timers 12.2.3 Time Constant Register B (TCORB) TCORB0 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORBX, TCORBY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORB is an 8-bit readable/writable register.
Section 12 8-Bit Timers 12.2.4 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which TCNT is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in hardware standby mode. For details of the timing, see section 12.3, Operation.
Section 12 8-Bit Timers Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.
Section 12 8-Bit Timers Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. The input clock can be selected from either six or three clocks, all divided from the system clock (φ). The falling edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges.
Section 12 8-Bit Timers TCR STCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description X Y 0 0 0 — — Clock input disabled (Initial value) 0 0 1 — — Counted on φ internal clock source 0 1 0 — — φ/2 internal clock source, counted on the falling edge 0 1 1 — — φ/4 internal clock source, counted on the falling edge 1 0 0 — — Clock input disabled 0 0 0 — — Clock input disabled 0 0 1 — — φ/4 internal clock source, counted on the falling edge
Section 12 8-Bit Timers 12.2.
Section 12 8-Bit Timers Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB Description 0 [Clearing conditions] 1 (Initial value) • Read CMFB when CMFB = 1, then write 0 in CMFB • When the DTC is activated by a CMIB interrupt [Setting condition] When TCNT = TCORB Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match.
Section 12 8-Bit Timers TCSR0 Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by compare-match A. Bit 4 ADTE Description 0 A/D converter start requests by compare-match A are disabled 1 A/D converter start requests by compare-match A are enabled (Initial value) TCSR1 Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Section 12 8-Bit Timers Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare-match of TCOR and TCNT. OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the effect of compare-match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: trigger output > 1 output > 0 output.
Section 12 8-Bit Timers 12.2.6 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and also selects the TCNT input clock.
Section 12 8-Bit Timers 12.2.7 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Section 12 8-Bit Timers Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2148 Group, some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2144 Group and H8S/2147N, there is no control of TMRY register access by this bit.
Section 12 8-Bit Timers 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function] Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is continually compared with the value in TCNT. When a match is detected, a compare-match C signal is generated.
Section 12 8-Bit Timers 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] Bit 7 6 5 4 3 2 1 0 — — — — — — — IS Initial value 1 1 1 1 1 1 1 0 Read/Write — — — — — — — R/W TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. TISR is initialized to H'FE by a reset and in hardware standby mode. Bits 7 to 1—Reserved: Do not write 0 to these bits.
Section 12 8-Bit Timers 12.2.13 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
Section 12 8-Bit Timers 12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock An internal clock created by dividing the system clock (φ) can be selected by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. φ Internal clock TCNT input clock TCNT N–1 N N+1 Figure 12.
Section 12 8-Bit Timers φ External clock input pin TCNT input clock TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA, CMFB) The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Section 12 8-Bit Timers Timer Output Timing When compare-match A or B occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare-match A. φ Compare-match A signal Timer output pin Figure 12.
Section 12 8-Bit Timers φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.7 Timing of Clearing by External Reset Input 12.3.4 Timing of Overflow Flag (OVF) Setting OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12.8 shows the timing of this operation. φ TCNT H'FF H'00 Overflow signal OVF Figure 12.8 Timing of OVF Setting 12.3.
Section 12 8-Bit Timers 16-Bit Count Mode When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. • Setting of compare-match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
Section 12 8-Bit Timers 12.3.6 Input Capture Operation TMRX has input capture registers of TICR, TICRR, and TICRF. Narrow pulse width can be measured with TICRR and TICRF, using one capture operation controlled by the ICST bit in the TCONRI register of the timer connection. When TMRIX detects a rising and falling edge successively after the ICST bit has been set to 1, the values of TCNT at that time are transferred to TICRR and TICRF and ICST bit is cleared to 0.
Section 12 8-Bit Timers TICRR, TICRF read cycle T1 T2 φ TMRIX Input capture signal Figure 12.10 Timing of Input Capture Signal (When Input Capture Input Signal Enters while TICRR and TICRF Are Being Read) (2) Input capture signal input selection Input capture input signal (TMRIX) in TMRX is switched by setting bits in the TCONRI register. Figure 12.11 and Table 12.3 show the input capture signal selections. See section 13.2.1, Timer Connection Register I (TCONRI), for details.
Section 12 8-Bit Timers Table 12.3 Input Capture Signal Selection TCONRI Bit 4 Bit 7 Bit 6 Bit 3 Bit 1 ICST SIMOD1 SIMOD0 HFINV HIINV Description 0 — — — — Input capture function not used 1 0 0 0 — TMIX pin input signal 1 — Inverted signal of TMIX pin input 1 1 12.
Section 12 8-Bit Timers Table 12.6 TMRY 8-Bit Timer Interrupt Sources Interrupt source Description DTC Activation Interrupt Priority CMIA Requested by CMFA Possible High CMIB Requested by CMFB Possible OVI Requested by OVF Not possible 12.5 Low 8-Bit Timer Application Example In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.12.
Section 12 8-Bit Timers 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows this operation.
Section 12 8-Bit Timers 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.14 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.14 Contention between TCNT Write and Increment Rev. 4.
Section 12 8-Bit Timers 12.6.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 12.15 shows this operation. With TMRX, an ICR input capture contends with a compare-match in the same way as with a write to TCORC. In this case, the input capture has priority and the compare-match signal is inhibited.
Section 12 8-Bit Timers 12.6.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.7. Table 12.7 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.6.
Section 12 8-Bit Timers Table 12.8 Switching of Internal Clock and TCNT Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low 1 to low* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 CKS bit rewrite 2 Switching from low 2 to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Rev. 4.
Section 12 8-Bit Timers No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high 3 to low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
Section 13 Timer Connection Section 13 Timer Connection Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N. 13.1 Overview The H8S/2148 Group allows interconnection between a combination of input signals, the input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels (TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output.
Rev. 4.00 Sep 27, 2006 page 378 of 1130 REJ09B0327-0400 Figure 13.
Section 13 Timer Connection 13.1.3 Input and Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.
Section 13 Timer Connection 13.1.4 Register Configuration Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed when the HIE bit in SYSCR is 0. Table 13.
Section 13 Timer Connection Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits select the signal source of the IHI and IVI signals.
Section 13 Timer Connection Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV): These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the vertical synchronization signal (VSYNCI).
Section 13 Timer Connection 13.2.2 Timer Connection Register O (TCONRO) Bit 7 6 5 4 3 2 HOE VOE CLOE CBOE HOINV VOINV 1 0 CLOINV CBOINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. TCONRO is initialized to H'00 by a reset and in hardware standby mode.
Section 13 Timer Connection Bit 5 CLOE Description 0 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin 1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin (Initial value) Bit 4 CBOE Description 0 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin 1 In mode 1 (expanded mode with on-chip ROM disabled): The P27/A15/PW15/CBLANK pin functions as the A15 pin (Initial value) In modes 2 and 3 (modes with on-chip ROM enabled): The P27/A15/PW15/CBLANK pin f
Section 13 Timer Connection Bit 0 CBOINV Description 0 The CBLANK signal is used directly as the CBLANK output 1 The CBLANK signal is inverted before use as the CBLANK output 13.2.
Section 13 Timer Connection Bits 5 and 4—Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1, HOMOD0): These bits select the signal source and generation method for the IHO signal.
Section 13 Timer Connection Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits select the signal source for the CLO signal (clamp waveform). Bit 6 Bit 1 Bit 0 ISGENE CLMOD1 CLMOD2 Description 0 0 0 The CL1 signal is selected 1 The CL2 signal is selected 0 The CL3 signal is selected 1 (Initial value) 1 1 0 0 The CL4 signal is selected 1 1 0 1 13.2.
Section 13 Timer Connection Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin. Bit 7 VEDG Description 0 [Clearing condition] (Initial value) When 0 is written in VEDG after reading VEDG = 1 1 [Setting condition] When a rising edge is detected on the VSYNCI pin Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
Section 13 Timer Connection Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin. Bit 3 VFEDG Description 0 [Clearing condition] (Initial value) When 0 is written in VFEDG after reading VFEDG = 1 1 [Setting condition] When a rising edge is detected on the VFBACKI pin Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH modification condition.
Section 13 Timer Connection Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. Bit 0 IVI Description 0 The IVI signal is low 1 The IVI signal is high 13.2.
Section 13 Timer Connection MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop mode. MSTPCRH Bit 4 MSTP12 Description 0 8-bit timer channel 0 and 1 module stop mode is cleared 1 8-bit timer channel 0 and 1 module stop mode is set (Initial value) MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer connection module stop mode.
Section 13 Timer Connection Table 13.3 Examples of TCR Settings Bit(s) Abbreviation Contents Description 7 CMIEB 0 6 CMIEA 0 Interrupts due to compare-match and overflow are disabled 5 OVIE 0 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (IHI signal) 2 to 0 CKS2 to CKS0 001 Incremented on internal clock: φ Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings φ:10 MHz φ: 12 MHz φ: 16 MHz φ: 20 MHz H'07 0.8 µs 0.67 µs 0.5 µs 0.
Section 13 Timer Connection 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMRX can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using TMRY.
Section 13 Timer Connection IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) IHI signal CL3 signal TCNT TICR+TCORC TICR Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.3.4 IHI Signal and 2fH Modification By using the timer connection FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection 13.3.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection FRT and TMRY, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant.
Section 13 Timer Connection Table 13.
Section 13 Timer Connection IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR OCRA FRC 6 system clocks 6 system clocks 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart Rev. 4.
Section 13 Timer Connection 13.3.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9. Table 13.
Section 13 Timer Connection 13.3.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10. Table 13.
Section 13 Timer Connection Mode IVI Signal IVO Signal Meaning of IVO Signal Separate mode VSYNCI input IVI signal (without fall modification or IHI synchronization) VSYNCI input (vertical synchronization signal) is output directly IVI signal (without fall modification, with IHI synchronization) Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) IVI signal (with fall modification, without IHI synchronization) VSY
Section 13 Timer Connection Rev. 4.
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) 14.1 Overview This LSI have an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring system operation. The WDT outputs an overflow signal (RESO) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 14 Watchdog Timer (WDT) 14.1.2 Block Diagram Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1. WOVI0 (interrupt request signal) RESO signal*1 Interrupt control Overflow Clock Clock select Reset control Internal reset signal*1 Internal clock source TCNT TCSR Module bus Bus interface Internal bus Internal NMI interrupt request signal*2 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 WDT0 Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1.
Section 14 Watchdog Timer (WDT) Internal NMI (interrupt request signal)*2 Interrupt control RESO signal*1 Overflow φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock select Clock Reset control Internal reset signal*1 Internal clock source TCNT φSUB/2 φSUB/4 φSUB/8 φSUB/16 φSUB/32 φSUB/64 φSUB/128 φSUB/256 TCSR Bus interface Module bus Internal bus WOVI1 (interrupt request signal) WDT1 Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1.
Section 14 Watchdog Timer (WDT) 14.1.4 Register Configuration The WDT has four registers, as summarized in table 14.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 14.
Section 14 Watchdog Timer (WDT) TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access. 14.2.
Section 14 Watchdog Timer (WDT) Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF Description 0 [Clearing conditions] 1 • Write 0 in the TME bit • Read TCSR when OVF = 1*, then write 0 in OVF (Initial value) [Setting condition] When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 14 Watchdog Timer (WDT) TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1. TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For details, see the description of the CKS2 to CKS0 bits below.
Section 14 Watchdog Timer (WDT) • WDT1 input clock selection Bit 4 Bit 2 Bit 1 Bit 0 PSS CKS2 CKS1 CKS0 Clock Overflow Period* (when φ = 20 MHz and φSUB = 32.768 kHz) 0 0 0 0 φ/2 (Initial value) 25.6 µs 1 φ/64 819.2 µs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.4 ms 1 φ/131072 1.68 s 0 φSUB/2 15.6 ms 1 φSUB/4 31.3 ms 0 φSUB/8 62.
Section 14 Watchdog Timer (WDT) read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by an internal reset due to watchdog timer overflow. Bit 3 XRST Description 0 Reset is generated by watchdog timer overflow 1 Reset is generated by external reset input 14.2.4 (Initial value) Notes on Register Access The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult to write to.
Section 14 Watchdog Timer (WDT) 14.3 Operation 14.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, an internal reset or NMI interrupt request is generated.
Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 H'00 written to TCNT OVF = 1* WT/IT = 1 H'00 written TME = 1 to TCNT RESO and internal reset generated RESO signal 132 system clock periods Internal reset signal Legend: WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag 518 system clock periods Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0. Figure 14.
Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 14.4 Operation in Interval Timer Mode 14.3.3 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5.
Section 14 Watchdog Timer (WDT) 14.3.4 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a low-level signal is output from the RESO pin. The timing is shown in figure 14.6. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal Internal reset signal 132 states 518 states Figure 14.6 RESO Signal Output Timing 14.
Section 14 Watchdog Timer (WDT) 14.5 Usage Notes 14.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.7 Contention between TCNT Write and Increment 14.5.
Section 14 Watchdog Timer (WDT) 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 14.5.4 System Reset by RESO Signal If the RESO output signal is input to the chip’s RES pin, the chip will not be initialized correctly.
Section 14 Watchdog Timer (WDT) Caution is therefore required when using WDT1 as the realtime clock counter. No error occurs in the counter value while WDT1 is operating in the same mode. 14.5.6 OVF Flag Clear Condition To clear OVF flag in WOVI handling routine, read TCSR when OVF = 1, then write with 0 to OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF.
Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) 15.1 Overview This LSI are equipped with a 3-channel serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Section 15 Serial Communication Interface (SCI, IrDA) Synchronous mode: Serial data communication is synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length: 8 bits Receive error detection: Overrun errors detected • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Do
Section 15 Serial Communication Interface (SCI, IrDA) 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI.
Section 15 Serial Communication Interface (SCI, IrDA) 15.1.3 Pin Configuration Table 15.1 shows the serial pins used by the SCI. Table 15.1 SCI Pins Channel Pin Name Symbol* I/O Function 0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output 1 2 Note: 15.1.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Register Descriptions 15.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU.
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.5 Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 0 1 stop bit* 2 2 stop bits* 1 1 (Initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 1 Bit 0 CKS1 CKS0 Description 0 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock 1 15.2.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Section 15 Serial Communication Interface (SCI, IrDA) external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out before the SCI’s operating mode is determined using SMR. For details of clock source selection, see table 15.9 in section 15.3, Operation.
Section 15 Serial Communication Interface (SCI, IrDA) SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description 0 [Clearing condition] 1 (Initial value)* When 0 is written in ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1* 2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 1—Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified.
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.8 Bit Rate Register (BRR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) φ = 2 MHz φ = 2.097152 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 150 1 103 0.16 1 300 0 207 0.16 600 0 103 1200 0 2400 4800 φ = 2.4576 MHz N Error (%) –0.04 1 174 108 0.21 1 0 217 0.21 0.16 0 108 0.21 51 0.16 0 54 0 25 0.16 0 0 12 0.
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) φ = 6 MHz Bit Rate (bits/s) n N Error (%) 110 2 106 150 2 300 φ = 6.144 MHz φ = 7.3728 MHz φ = 8 MHz N Error (%) n N Error (%) –0.44 2 108 0.08 2 130 77 0.16 2 79 0.00 2 1 155 0.16 1 159 0.00 1 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.
Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) φ = 14 MHz φ = 14.7456 MHz Bit Rate (bits/s) n N Error (%) 110 2 248 150 2 300 φ = 16 MHz φ = 17.2032 MHz N Error (%) n N Error (%) n N Error (%) –0.17 3 64 0.70 3 70 0.03 3 75 0.48 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode) Operating Frequency φ (MHz) φ = 2 MHz Bit Rate φ = 4 MHz (bits/s) n N n N 110 3 70 — — 250 2 124 2 500 1 249 2 1k 1 124 2.
Section 15 Serial Communication Interface (SCI, IrDA) The BRR setting is found from the following equations. Asynchronous mode: N= φ 64 × 22n–1 ×B × 106 – 1 Synchronous mode: N= Where B: N: φ: n: φ × 106 – 1 8 × 22n–1 × B Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 15.2.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR.
Section 15 Serial Communication Interface (SCI, IrDA) Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode. MSTPCRL Bit 7 MSTP7 Description 0 SCI0 module stop mode is cleared 1 SCI0 module stop mode is set (Initial value) Bit 6—Module Stop (MSTP6): Specifies the SCI1 module stop mode. MSTPCRL Bit 6 MSTP6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set (Initial value) Bit 5—Module Stop (MSTP5): Specifies the SCI2 module stop mode.
Section 15 Serial Communication Interface (SCI, IrDA) 15.2.11 Keyboard Comparator Control Register (KBCOMP) 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KBCOMP is an 8-bit readable/writable register that selects the functions of SCI2 and the A/D converter. KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 15.8.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
Section 15 Serial Communication Interface (SCI, IrDA) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR. Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0.
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
Section 15 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.7 Sample Serial Reception Data Flowchart (cont) Rev. 4.
Section 15 Serial Communication Interface (SCI, IrDA) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a.
Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: receiving station specification (MPB = 0) Data transmission cycle: data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled.
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 15 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 Multiprocessor Stop bit bit Data D0 D1 D7 0/1 1 Start bit 0 Multiproces- Stop 1 sor bit bit Data D0 D1 D7 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 15.
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start reception Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev. 4.
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.13 shows an example of SCI operation for multiprocessor format reception.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Section 15 Serial Communication Interface (SCI, IrDA) [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used.
Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Section 15 Serial Communication Interface (SCI, IrDA) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.17 Example of SCI Operation in Transmission Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial reception.
Section 15 Serial Communication Interface (SCI, IrDA) [1] Initialization Start reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error handling (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI, IrDA) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI, IrDA) 15.3.5 IrDA Operation Figure 15.21 shows a block diagram of the IrDA function. When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins).
Section 15 Serial Communication Interface (SCI, IrDA) The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set as the minimum high-level pulse width at 1.41 µs or above. When the serial data is 1, no pulse is output.
Section 15 Serial Communication Interface (SCI, IrDA) High-Level Pulse Width Selection Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 Bit IrCKS2 to IrCKS0 Settings Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.
Section 15 Serial Communication Interface (SCI, IrDA) 15.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR.
Section 15 Serial Communication Interface (SCI, IrDA) TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. 15.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR.
Section 15 Serial Communication Interface (SCI, IrDA) Break Detection and Processing When a framing error (FER) is detected, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
Section 15 Serial Communication Interface (SCI, IrDA) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by equation (1) below. M = 0.5 – Where M: N: D: L: F: 1 D – 0.5 (1 + F) × 100% – (L – 0.5)F – 2N N ..........
Section 15 Serial Communication Interface (SCI, IrDA) Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24) • When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI).
2 Section 16 I C Bus Interface [Option] 2 Section 16 I C Bus Interface [Option] 2 A two-channel I C bus interface is available as an option in the H8S/2148 Group and H8S/2147N. 2 The I C bus interface is not available for the H8S/2144 Group. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432147SWFA 2. The product number is identical for F-ZTAT versions.
2 Section 16 I C Bus Interface [Option] • Wait function in slave mode (I C bus format) 2 A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible.
2 Section 16 I C Bus Interface [Option] Formatless dedicated clock (channel 0 only) φ PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Interrupt generator Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Second slav
2 Section 16 I C Bus Interface [Option] Vcc VCC SCL SCL SDA SDA SCL in SDA in SCL SDA SDA out (Master) SCL in H8S/2148 Group and H8S/2147N chip SCL out SCL out SDA in SDA in SDA out SDA out SCL SDA SCL out SCL in (Slave 1) (Slave 2) 2 Figure 16.2 I C Bus Interface Connections (Example: H8S/2148 Group and H8S/2147N Chip as Master) 16.1.3 Input/Output Pins 2 Table 16.1 summarizes the input/output pins used by the I C bus interface. 2 Table 16.
2 Section 16 I C Bus Interface [Option] 16.1.4 Register Configuration 2 Table 16.2 summarizes the registers of the I C bus interface. Table 16.
2 Section 16 I C Bus Interface [Option] 16.2 Register Descriptions 16.2.
2 Section 16 I C Bus Interface [Option] ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
2 Section 16 I C Bus Interface [Option] TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started (Initial value) [Clearing conditions] • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) • When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected • When a stop condition is detected with the I C bus format selected • In receive mode (TRS = 0) 2 (A 0 w
2 Section 16 I C Bus Interface [Option] 16.2.2 Slave Address Register (SAR) Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format.
2 Section 16 I C Bus Interface [Option] DDCSWR Bit 6 SAR Bit 0 SARX Bit 0 SW FS FSX Operating Mode 0 0 0 I C bus format 2 • 1 I C bus format • SAR slave address recognized • SARX slave address ignored 0 I C bus format • SAR slave address ignored • SARX slave address recognized Synchronous serial format • 16.2.
2 Section 16 I C Bus Interface [Option] Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to 2 SVAX0, differing from the addresses of other slave devices connected to the I C bus. Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format.
2 Section 16 I C Bus Interface [Option] Bit 7 MLS Description 0 MSB-first 1 LSB-first (Initial value) Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data 2 and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
2 Section 16 I C Bus Interface [Option] Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate.
2 Section 16 I C Bus Interface [Option] Bit 2 Bit 1 Bit 0 BC2 BC1 BC0 Synchronous Serial Format I C Bus Format 0 0 0 8 9 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 1 1 0 1 Bits/Frame 2 (Initial value) 2 16.2.5 I C Bus Control Register (ICCR) Bit 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/(W)* W Note: * Only 0 can be written, to clear the flag.
2 Section 16 I C Bus Interface [Option] Bit 7 ICE Description 0 I C bus interface module disabled, with SCL and SDA signal pins set to port function (Initial value) 2 2 I C bus interface module internal states initialized SAR and SARX can be accessed 2 1 I C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed 2 2 Bit 6—I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C bus interface to the CP
2 Section 16 I C Bus Interface [Option] Bit 5 Bit 4 MST TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 (Initial value) Bit 5 MST Description 0 Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2 2. When bus arbitration is lost after transmission is started in I C bus format master mode 1 Master mode [Setting conditions] 1.
2 Section 16 I C Bus Interface [Option] Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the 2 acknowledge bit returned from the receiving device when using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0.
2 Section 16 I C Bus Interface [Option] Bit 2 BBSY Description 0 Bus is free (Initial value) [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected 2 2 Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has issued an interrupt request to the CPU.
2 Section 16 I C Bus Interface [Option] Bit 1 IRIC 0 Description Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) 1 Interrupt requested [Setting conditions] • I2C bus format master mode 1.
2 Section 16 I C Bus Interface [Option] 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
2 Section 16 I C Bus Interface [Option] Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored.
2 Section 16 I C Bus Interface [Option] Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been 2 detected during frame transfer in I C bus format slave mode. Bit 7 ESTP Description 0 No error stop condition (Initial value) [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2.
2 Section 16 I C Bus Interface [Option] IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Bit 5 IRTR Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2.
2 Section 16 I C Bus Interface [Option] Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The 2 I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at 2 nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL.
2 Section 16 I C Bus Interface [Option] Bit 2 AAS Description 0 Slave address or general call address not recognized (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AAS after reading AAS = 1 3.
2 Section 16 I C Bus Interface [Option] Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read.
2 Section 16 I C Bus Interface [Option] 2 Bit 7—I C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of 2 output buffer as SCL and SDA. This bit is used when implementing the I C interface by software only.
2 Section 16 I C Bus Interface [Option] 16.2.8 DDC Switch Register (DDCSWR) Bit 7 6 5 4 3 2 1 0 SWE SW IE IF CLR3 CLR2 CLR1 CLR0 Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/(W)*1 W*2 W*2 W*2 W*2 Notes: 1. Only 0 can be written, to clear the flag. 2. Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize IIC and controls IIC internal latch clearance. DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
2 Section 16 I C Bus Interface [Option] Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when automatic format switching is executed for IIC channel 0.
2 Section 16 I C Bus Interface [Option] Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 Description 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 0 IIC1 internal latch cleared 1 IIC0 and IIC1 internal latches cleared — Invalid setting 1 1 — 16.2.
2 Section 16 I C Bus Interface [Option] MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode. MSTPCRL Bit 3 MSTP3 Description 0 IIC channel 1 module stop mode is cleared 1 IIC channel 1 module stop mode is set 16.3 Operation 16.3.1 I C Bus Data Format (Initial value) 2 2 2 The I C bus interface has serial and I C bus formats. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 16.3 (a) and (b).
2 Section 16 I C Bus Interface [Option] (a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 Legend: n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 Legend: n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) 2
2 Section 16 I C Bus Interface [Option] SDA SCL S 1-7 8 9 SLA R/W A 1-7 8 DATA 9 A 1-7 8 DATA 9 A/A P 2 Figure 16.6 I C Bus Timing 2 Table 16.4 I C Bus Data Format Symbols Legend S Start condition.
2 Section 16 I C Bus Interface [Option] (6) Write data to ICDR (slave address + R/W) 2 With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. Then clear the IRIC flag to indicate the end of transfer. Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no interrupt is inserted.
2 Section 16 I C Bus Interface [Option] Start condition generation SCL (master output) 1 SDA (master output) bit 7 2 bit 6 3 bit 5 4 bit 4 5 6 bit 3 bit 2 bit 1 8 1 9 2 bit 7 bit 0 R/W Slave address SDA (slave output) 7 [7] bit 6 Data 1 A [5] IRIC IRTR ICDR address + R/W Note: Data write timing in ICDR ICDR Writing prohibited Data 1 ICDR Writing enable User processing [4] Write BBSY = 1 and SCP = 0 (start condition issuance) [6] ICDR write [6] IRIC clear [9] ICDR write [9]
2 Section 16 I C Bus Interface [Option] (3) The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. If the first frame is the final reception frame, execute the end processing as described in (l0). (4) Clear the IRIC flag to 0 to release from the wait state.
2 Section 16 I C Bus Interface [Option] Master transmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data 1 9 [3] SDA (master output) 1 2 Bit7 Bit6 3 4 5 Bit5 Bit4 Bit3 Data 2 [5] A IRIC IRTR ICDR Data 1 [2] IRIC clear [1] TRS cleared to 0 [2] ICDR read (dummy read) WAIT set to 1 ACKB cleared to 0 User processing [4] IRIC clear [6] ICDR read (Data 1) [7] IRIC clear Figure 16.
2 Section 16 I C Bus Interface [Option] 16.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode.
2 Section 16 I C Bus Interface [Option] Start condition generation SCL (master output) 1 2 3 Bit 7 Bit 6 Bit 5 4 5 6 Bit 4 Bit 3 Bit 2 7 8 9 1 2 SCL (slave output) SDA (master output) Slave address SDA (slave output) Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 [4] A RDRF IRIC Interrupt request generation ICDRS Address + R/W ICDRR User processing Address + R/W [5] ICDR read [5] IRIC clear Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 4.
2 Section 16 I C Bus Interface [Option] SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 3 4 5 6 7 8 9 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCL (slave output) SDA (master output) Data 1 SDA (slave output) Bit 7 Bit 6 [4] Data 2 A [4] A RDRF IRIC ICDRS Data 1 ICDRR Data 1 User processing Interrupt request generation Interrupt request generation [5] ICDR read Data 2 Data 2 [5] IRIC clear Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) Rev.
2 Section 16 I C Bus Interface [Option] 16.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode.
2 Section 16 I C Bus Interface [Option] Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 2 3 4 5 6 7 8 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 SCL (slave output) SDA (slave output) SDA (master output) R/W Bit 7 Data 1 [2] Bit 6 Data 2 A TDRE Interrupt request generation IRIC [3] Interrupt request generation Interrupt request generation Data 1 ICDRT ICDRS Data 2 Data 1 User processing [3] IRIC clear [3] ICDR write [3] ICDR write Dat
2 Section 16 I C Bus Interface [Option] 16.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.12 shows the IRIC set timing and SCL control.
2 Section 16 I C Bus Interface [Option] 16.3.7 2 Automatic Switching from Formatless Mode to I C Bus Format Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating 2 mode. Switching from formatless mode to the I C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin.
2 Section 16 I C Bus Interface [Option] 16.3.8 Operation Using the DTC 2 The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.5 shows some examples of processing using the DTC.
2 Section 16 I C Bus Interface [Option] 16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
2 Section 16 I C Bus Interface [Option] Start [1] Initialize Initialize [2] Test the status of the SCL and SDA lines. Read BBSY in ICCR No BBSY = 0? Yes [3] Select master transmit mode. Set MST = 1 and TRS = 1 in ICCR [4] Start condition issuance Write BBSY = 1 and SCP = 0 in ICCR [5] Wait for a start condition generation Read IRIC in ICCR No IRIC = 1? Yes [6] Set transmit data for the first byte (slave address + R/W).
2 Section 16 I C Bus Interface [Option] Master receive operation Set TRS = 0 in ICCR [1] Select receive mode Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. Read ICDR Clear IRIC in ICCR [3] Wait for 1 byte to be received. (8th clock falling edge) Read IRIC in ICCR No IRIC = 1? Yes Last receive ? Yes No No Clear IRIC in ICCR [4] Clear IRIC to trigger the 9th clock.
2 Section 16 I C Bus Interface [Option] Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR [2] No IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). Clear IRIC in ICCR [3] Start receiving.
2 Section 16 I C Bus Interface [Option] Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR [1] [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Clear IRIC in ICCR [3] Test for end of transfer. [4] Select slave receive mode. Read IRIC in ICCR No [2] [5] Dummy read (to release the SCL line).
2 Section 16 I C Bus Interface [Option] 16.3.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2) clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.2.8, DDC Switch Register (DDCSWR).
2 Section 16 I C Bus Interface [Option] The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1.
2 Section 16 I C Bus Interface [Option] 2 Table 16.6 I C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit Notes SCL output cycle time tSCLO 28tcyc to 256tcyc ns SCL output high pulse width tSCLHO 0.5tSCLO ns Figure 26.28 (reference) SCL output low pulse width tSCLLO 0.5tSCLO ns SDA output bus free time tBUFO 0.5tSCLO –1tcyc ns Start condition output hold time tSTAHO 0.
2 Section 16 I C Bus Interface [Option] Table 16.7 Permissible SCL Rise Time (tSr) Values Time Indication 2 I C Bus Specification φ = (Max.) 5 MHz tcyc IICX Indication 0 1 7.5tcyc 17.
2 Section 16 I C Bus Interface [Option] 2 Table 16.8 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 Item tSCLHO tSCLLO tBUFO tcyc Indication 0.5tSCLO (–tSr) 0.5tSCLO (–tSf ) Standard mode I C Bus SpecifitSr/tSf Influence cation φ = (Max.) (Min.
2 Section 16 I C Bus Interface [Option] Time Indication (at Maximum Transfer Rate) [ns] 2 Item tcyc Indication tSDAHO 3tcyc I C Bus SpecifitSr/tSf Influence cation φ = (Max.) (Min.) 5 MHz φ= 8 MHz φ= φ= φ= 10 MHz 16 MHz 20 MHz 0 0 600 375 300 188 150 High-speed 0 mode 0 600 375 300 188 150 Standard mode 2 Notes: 1. Does not meet the I C bus interface specification.
2 Section 16 I C Bus Interface [Option] Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register).
2 Section 16 I C Bus Interface [Option] [1] Wait for end of 1-byte transfer IRIC = 1 ? No [1] [2] Determine whether SCL is low Yes Clear IRIC in ICSR Start condition issuance? [3] Issue restart condition instruction for retransmission [4] Determine whether start condition is generated or not No Other processing [5] Set transmit data (slave address + R/W) Yes SCL = Low ? Note: Program so that processing from [3] to [5] is executed continuously.
2 Section 16 I C Bus Interface [Option] • Notes on I C Bus Interface Stop Condition Instruction Issuance 2 If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition instruction after reading SCL and determining it to be low, as shown below.
2 Section 16 I C Bus Interface [Option] • Notes on WAIT Function Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall.
2 Section 16 I C Bus Interface [Option] • Notes on ICDR Reads and ICCR Access in Slave Transmit Mode 2 In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 16.22.
2 Section 16 I C Bus Interface [Option] • Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23) 2 in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 16.
2 Section 16 I C Bus Interface [Option] • Notes on Arbitration Lost in Master Mode 2 The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address.
2 Section 16 I C Bus Interface [Option] (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. • Notes on Interrupt Occurrence after ACKB Reception Conditions to cause this failure The IRIC flag is set to 1 when both of the following conditions are satisfied.
2 Section 16 I C Bus Interface [Option] Master transmit mode or slave transmit mode Stop condition Slave reception mode Start condition (2) Address that does not match is received. SDA N SCL 8 Address 1 9 2 3 4 5 6 7 8 A Data 9 1 2 ACKB bit IRIC flag Stop condition detection (1) Acknowledge bit is received and the ACKB bit is set to 1. Countermeasure: Clear the ACKE bit to 0 to clear the ACKB bit. (3) Unnecessary interrupt occurs (received address is invalid). Figure 16.
2 Section 16 I C Bus Interface [Option] • Notes on TRS Bit Setting and ICDR Register Access Conditions to cause this failure Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are satisfied. Master mode Figure 16.26 shows the notes on ICDR reading (TRS = 1) in master mode. (1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full). (2) Reads ICDR register after switching to transmit mode (TRS = 1).
2 Section 16 I C Bus Interface [Option] Along with ICDRS: ICDRR transfer Stop condition SDA Cancel condition of SCL = Low fixation is set. Start condition Address A SCL 8 1 9 2 3 4 5 6 7 8 A Data 9 1 2 3 (3) TRS = 0 TRS bit (2) RDRF = 0 RDRF bit ICDRS data full (1) ICDRS data full TRS = 0 setting ICDR read Detection of 9th clock rise (TRS = 1) Figure 16.
2 Section 16 I C Bus Interface [Option] Rev. 4.
Section 17 Keyboard Buffer Controller Section 17 Keyboard Buffer Controller Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group. 17.1 Overview The H8S/2148 Group and H8S/2147N have three on-chip keyboard buffer controller channels, designated 0, 1, and 2. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications.
Section 17 Keyboard Buffer Controller Vcc Vcc System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer controller (H8S/2148 Group and H8S/2147N chip) I/F Figure 17.1 Keyboard Buffer Controller Connection Rev. 4.
Section 17 Keyboard Buffer Controller 17.1.2 Block Diagram Figure 17.2 shows a block diagram of the keyboard buffer controller. Internal data bus KCLK (PS2AC, PS2BC, PS2CC) KDI Control logic KCLKI KBCRH Parity Bus interface KD (PS2AD, PS2BD, PS2CD) Module data bus KBBR KDO KCLKO KBCRL Register counter value KB interrupt Legend: KD: KCLK: KBBR: KBCRH: KBCRL: KBC data I/O pin KBC clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L Figure 17.
Section 17 Keyboard Buffer Controller 17.1.3 Input/Output Pins Table 17.1 lists the input/output pins used by the keyboard buffer controller. Table 17.
Section 17 Keyboard Buffer Controller 17.2 Register Descriptions 17.2.1 Keyboard Control Register H (KBCRH) Bit 7 6 5 4 3 2 1 0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS Initial value 0 1 1 1 0 0 0 0 Read/Write R/W R R R/W R/W R/(W)* R/(W)* R Note: * Only 0 can be written, to clear the flags. KBCRH is an 8-bit readable/writable register that indicates the operating status of the keyboard buffer controller.
Section 17 Keyboard Buffer Controller Bit 5—Keyboard Data In (KDI): Monitors the KDI I/O pin. This bit cannot be modified. Bit 5 KDI Description 0 KD I/O pin is low 1 KD I/O pin is high (Initial value) Bit 4—Keyboard Buffer Register Full Select (KBFSEL): Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag, When KBFSEL is cleared to 0, the KBE bit in the KBCRL register should be cleared to 0 to disable reception.
Section 17 Keyboard Buffer Controller Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred. Bit 1 PER Description 0 [Clearing condition] (Initial value) Read PER when PER =1, then write 0 in PER 1 [Setting condition] When an odd parity error occurs Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1. Bit 0 KBS Description 0 0 stop bit received 1 1 stop bit received 17.2.
Section 17 Keyboard Buffer Controller Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output. Bit 6 KCLKO Description 0 Keyboard buffer controller clock I/O pin is low 1 Keyboard buffer controller clock I/O pin is high (Initial value) Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output.
Section 17 Keyboard Buffer Controller 17.2.3 Keyboard Data Buffer Register (KBBR) Bit 7 6 5 4 3 2 1 0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1. KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0. 17.2.
Section 17 Keyboard Buffer Controller 17.3 Operation 17.3.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on the H8S/2148 Group chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4. Rev. 4.
Section 17 Keyboard Buffer Controller Start Set KBIOE bit [1] Read KBCRH [2] KCLKI and KDI bits both 1? No Yes Set KBE bit [3] [1] Set the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). Keyboard side in data transmission state. Execute receive abort processing. [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK.
Section 17 Keyboard Buffer Controller Receive processing/ error handling KCLK (pin state) 1 KD (pin state) Start bit 2 0 3 1 9 7 10 Flag cleared 11 Parity bit Stop bit KCLK (input) KCLK (output) Automatic I/O inhibit KB7 to KB0 Previous data KB0 KB1 Receive data PER KBS KBF [1] [2] [3] [4] [5] [6] Figure 17.4 Receive Timing 17.3.
Section 17 Keyboard Buffer Controller Start Set KBIOE bit [1] Read KBCRH [2] KCLKI and KDI bits both 1? Yes Set I/O inhibit (KCLKO = 0) [1] Set the KBE bit to 1 in KBCRH, and the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). No 2 [3] Write 0 in the KBE bit (disable KBBR receive operation). KDO remains at 1 [4] Write 0 in the KDO bit (set start bit).
Section 17 Keyboard Buffer Controller 1 Read KBCRH No KCLKI = 0? 2 Yes * [7] No KDI = 0? Keyboard side in data transmission state. Execute receive abort processing. Yes [8] Read KBCRH Error handling No KCLK = 1? Yes Transmit end state (KCLK = high, KD = high) To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 17.
Section 17 Keyboard Buffer Controller 17.3.3 Receive Abort The H8S/2148 Group and H8S/2147N device (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high.
Section 17 Keyboard Buffer Controller [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation.
Section 17 Keyboard Buffer Controller Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = H) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 17.7 Sample Receive Abort Processing Flowchart (cont) Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period.
Section 17 Keyboard Buffer Controller 17.3.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. T1 T2 φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.9 KCLKI and KDI Read Timing Rev. 4.
Section 17 Keyboard Buffer Controller 17.3.5 KCLKO and KDO Write Timing Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 T2 φ* Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.10 KCLKO and KDO Write Timing Rev. 4.
Section 17 Keyboard Buffer Controller 17.3.6 KBF Setting Timing and KCLK Control Figure 17.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK (pin) 11th fall Internal KCLK Falling edge signal RXCR3 to RXCR0 H'010 H'000 KBF KCLK (output) Automatic I/O inhibit Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 4.
Section 17 Keyboard Buffer Controller 17.3.7 Receive Timing Figure 17.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 N N+1 N+2 Internal KD (KDI) KBBR7 to KBBR0 Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.12 Receive Counter and KBBR Data Load Timing Rev. 4.
Section 17 Keyboard Buffer Controller 17.3.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.13 shows the setting method and an example of operation.
Section 17 Keyboard Buffer Controller 17.3.9 Usage Note When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the timing of KBIOE setting and KCLK falling edge detection.
Section 17 Keyboard Buffer Controller Rev. 4.
Section 18 Host Interface Section 18 Host Interface Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group. 18.1 Overview The H8S/2148 Group and H8S/2147N have an on-chip host interface (HIF) that enables connection to an ISA bus, widely used as the internal bus in personal computers. The host interface provides a four-channel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HI12E bit is set to 1 in SYSCR2.
Section 18 Host Interface 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the host interface.
Section 18 Host Interface 18.1.3 Input and Output Pins Table 18.1 lists the input and output pins of the host interface module. Table 18.
Section 18 Host Interface 18.1.4 Register Configuration Table 18.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1, ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR. Table 18.
Section 18 Host Interface 18.2 Register Descriptions 18.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W SYSCR is an 8-bit readable/writable register which controls H8S/2148 Group chip operations. Of the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed when the HIE bit is set to 1.
Section 18 Host Interface Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2) can be accessed. Bit 1 HIE Description 0 Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is disabled (Initial value) 1 Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is enabled 18.2.
Section 18 Host Interface Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function. When this function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin.
Section 18 Host Interface 18.2.
Section 18 Host Interface HICR2 Bit 2 HICR2 Bit 1 HICR Bit 2 HICR Bit 1 IBFIE4 IBFIE3 IBFIE2 IBFIE1 Description — — — 0 Input data register (IDR1) reception completed interrupt request disabled (Initial value) — — — 1 Input data register (IDR1) reception completed interrupt request enabled — — 0 — Input data register (IDR2) reception completed interrupt request disabled (Initial value) — — 1 — Input data register (IDR2) reception completed interrupt request enabled — 0 — — I
Section 18 Host Interface 18.2.4 Input Data Register 1 (IDR1) Bit 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value — — — — — — — — Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CSn (n = 1 to 4) is low, information on the host data bus is written into IDRn at the rising edge of IOW.
Section 18 Host Interface 18.2.6 Status Register (STR) Bit Initial value 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R/(W)* Host Read/Write R R R R R R R R Note: * Only 0 can be written, to clear the flag. STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
Section 18 Host Interface Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR. Bit 0 OBF Description 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value) 1 [Setting condition] When the slave processor writes to ODR Table 18.3 shows the conditions for setting and clearing the STR flags. Table 18.
Section 18 Host Interface 18.2.7 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
Section 18 Host Interface Table 18.4 Host Interface Channel Selection and Pin Operation HI12E CS2E CS3E CS4E Operation 0 — — — Host interface functions halted 1 0 0 0 Host interface channel 1 only operating Operation of channels 2 to 4 halted (No operation as CS2 or ECS2, CS3, and CS4 inputs. Pins P43, P81, P90, and PB0 to PB3 operate as I/O ports.) 1 Host interface channel 1 and 4 functions operating Operation of channels 2 and 3 halted (No operation as CS2 or ECS2 and CS3 inputs.
Section 18 Host Interface 18.3.2 Control States Table 18.5 shows host interface operations from the HIF host, and slave operation. Table 18.
Section 18 Host Interface this pin by sending commands and data. This function is available only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 18.6 lists the conditions that set and clear GA20 (P81).
Section 18 Host Interface Table 18.
Section 18 Host Interface Table 18.8 shows the scope of HIF pin shutdown in slave mode. Table 18.
Section 18 Host Interface 18.4 Interrupts 18.4.1 IBF1, IBF2, IBF3, IBF4 The host interface can issue two interrupt requests to the slave CPU: IBF1, IBF2, IBF3, and IBF4. They are input buffer full interrupts for input data registers IDR1, IDR2, IDR3, and IDR4 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 18.
Section 18 Host Interface Table 18.
Section 18 Host Interface HIRQ Setting/Clearing Contention If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is executed after completion of the read/write. 18.5 Usage Note The following points require attention when using the host interface.
Section 18 Host Interface Rev. 4.
Section 19 D/A Converter Section 19 D/A Converter 19.1 Overview This LSI have an on-chip D/A converter module with two channels. 19.1.1 Features Features of the D/A converter module are listed below. • Eight-bit resolution • Two-channel output • Maximum conversion time: 10 µs (with 20-pF load capacitance) • Output voltage: 0 V to AVref • D/A output retention in software standby mode Rev. 4.
Section 19 D/A Converter 19.1.2 Block Diagram Module data bus Bus interface Figure 19.1 shows a block diagram of the D/A converter. AVref DACR 8-bit D/A DADR1 DA0 DADR0 AVCC DA1 AVSS Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 19.1 Block Diagram of D/A Converter Rev. 4.
Section 19 D/A Converter 19.1.3 Input and Output Pins Table 19.1 lists the input and output pins used by the D/A converter module. Table 19.
Section 19 D/A Converter 19.2 Register Descriptions 19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin.
Section 19 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 is disabled 1 D/A conversion is enabled on channel 0. Analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1.
Section 19 D/A Converter 19.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
Section 19 D/A Converter 19.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 19.2 shows the timing.
Section 19 D/A Converter Rev. 4.
Section 20 A/D Converter Section 20 A/D Converter 20.1 Overview This LSI incorporate a 10-bit successive-approximations A/D converter that allows up to eight analog input channels to be selected. In addition to the eight analog input channels, up to 16 channels of digital input can be selected for A/D conversion. Since the conversion precision falls when digital input is selected, digital input is ideal for use by a comparator identifying multi-valued inputs, for example. 20.1.
Section 20 A/D Converter 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter.
Section 20 A/D Converter 20.1.3 Pin Configuration Table 20.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 20.
Section 20 A/D Converter 20.1.4 Register Configuration Table 20.2 summarizes the registers of the A/D converter. Table 20.
Section 20 A/D Converter The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 20.3. The ADDR registers can always be read by the CPU.
Section 20 A/D Converter Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Section 20 A/D Converter Bit 4 SCAN Description 0 Single mode 1 Scan mode (Initial value) Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while ADST = 0. Bit 3 CKS Description 0 Conversion time = 266 states (max.) 1 Conversion time = 134 states (max.) (Initial value) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channel(s). One analog input channel can be switched to digital input.
Section 20 A/D Converter 20.2.3 A/D Control Register (ADCR) 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — — — — — Bit Initial value 0 0 1 1 1 1 1 1 Read/Write R/W R/W — — — — — — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
Section 20 A/D Converter 20.2.4 Keyboard Comparator Control Register (KBCOMP) Bit 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KBCOMP is an 8-bit readable/writable register that controls the SCI2 IrDA function and selects the CIN input channels for A/D conversion. KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Section 20 A/D Converter 20.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
Section 20 A/D Converter 20.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
Section 20 A/D Converter 20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 20.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
Section 20 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 20.
Section 20 A/D Converter 20.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately.
Section 20 A/D Converter Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 4 A/D conversion result 1 ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1.
Section 20 A/D Converter 20.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D conversion timing. Table 20.4 indicates the A/D conversion time. As indicated in figure 20.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR.
Section 20 A/D Converter Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay tD 10 — 17 6 — 9 Input sampling time tSPL — 63 — — 31 — A/D conversion time tCONV 259 — 266 131 — 134 Note: Values in the table are the number of states. 20.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Section 20 A/D Converter 20.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVref (n = 0 to 7). 2. Digital input voltage range The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVref and VSS ≤ CINn ≤ VCC (n = 0 to 15). 3.
Section 20 A/D Converter Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 20.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise.
Section 20 A/D Converter 10 kΩ AN0 to AN7 To A/D converter 20 pF Note: Numeric values are reference values. Figure 20.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions The A/D conversion precision in this LSI is defined as follows.
Section 20 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 20.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 20.10 A/D Conversion Precision Definitions (2) Rev. 4.
Section 20 A/D Converter Permissible Signal Source Impedance Analog input in this LSI is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ (AVcc = 4.0 to 5.5 V, when φ ≤ 12 MHz) or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ (AVcc = 4.0 to 5.
Section 21 RAM Section 21 RAM 21.1 Overview The H8S/2148, H8S/2144, and H8S/2143 have 4 kbytes of on-chip high-speed static RAM, and the H8S/2147, H8S/2147N, and H8S/2142 have 2 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 21.1.
Section 21 RAM 21.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration. Table 21.1 Register Configuration Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'09 H'FFC4 Note: 21.2 * Lower 16 bits of the address.
Section 21 RAM 21.3 Operation 21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1)) When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM.
Section 21 RAM Rev. 4.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.1 Overview The H8S/2148 and H8S/2144 have 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2143 has 96 kbytes, the H8S/2147, H8S/2147N, and H8S/2142 have 64 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.1.2 Register Configuration This group on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 22.1. Table 22.1 ROM Register Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined Depends on the operating mode H'FFC5 Note: * Lower 16 bits of the address. 22.2 Register Descriptions 22.2.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.4 Overview of Flash Memory 22.4.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.4.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.4.3 Flash Memory Operating Modes Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 22.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) On-Board Programming Modes • Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. 2.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) • User program mode 1. Initial state (1) The program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Differences between Boot Mode and User Program Mode Entire memory erase Boot Mode User Program Mode Yes Yes Block erase No Yes Programming control program* Program/program-verify Program/program-verify Erase/erase-verify Note: * To be provided by the user, in accordance with the recommended algorithm.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 22.3. Table 22.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.5 Register Descriptions 22.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When SWE = 1, and PSU = 1 22.5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 22.8.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit 7 6 5 4 3 2 1 0 EBR1 — — — — — — EB9/—* EB8/—* Initial value 0 0 0 0 0 0 Read/Write — — — — — — 0 0 1 2 1 2 * * R/W R/W* * Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write 1 R/W* R/W R/W R/W R/W R/W R/W R/W EBR2 2 2 Notes: 1.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate MCU measures low period of H'00 data transmitted by host MCU calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 Low period (9 bits) measured (H'00 data) D7 Stop bit High period (1 or more bits) Figure 22.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment When boot mode is initiated, this group MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) On-Chip RAM Area Divisions in Boot Mode In boot mode, the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 22.10. The area to which the programming control program is transferred is H'(FF)E080 to H'(FF)EFFF (3968 bytes) in the 128-kbyte versions, or H'(FF)E880 to H'(FF)EFFF (1920 bytes) in the 64-kbyte versions.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) µs. 22.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Start Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 22.13. The wait times (x, y, z, α, β, γ, ε, η) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N), see section 26.2.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Start *1 Set SWE bit in FLMCR1 Wait (x) µs *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *5 Clear ESU bit in FLMCR2 Wait (β) µs *5 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *5 Set block start address to verify address H'FF dummy write to verify address
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.9 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes — Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection 22.8.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Program mode Erase mode Reset or hardware standby (hardware protection) RES = 0 or STBY = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence*2 RES = 0 or STBY = 0 RES = 0 or STBY = 0 Error occurrence*1 Error protection mode RD VF*4 PR ER FLER = 1 Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible Software standby, sleep, subsleep
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased 1 (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation. There are three reasons for this: 1.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.10 Flash Memory Programmer Mode 22.10.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 1281 3 2 3 kbyte* * or 64-kbyte* * on-chip flash memory.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.10.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory. Figure 22.15 shows the memory map in programmer mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.11 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE FO0 to FO7 FA0 to FA17 Read L L H Data output Ain Output disable L H H Hi-Z X Command write 1 Chip disable* L H L Data input Ain* H X X Hi-Z X 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.13 AC Characteristics in Memory Read Mode Conditions: VCC = 5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.14 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.15 AC Characteristics in Memory Read Mode Conditions: VCC = 5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.10.5 Auto-Program Mode AC Characteristics Table 22.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Address stable FA17 to FA0 tceh CE tas tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf tds tdh Programming normal end identification signal FO6 Programming wait FO7 to FO0 H'40 Data Data FO0 to FO5 = 0 Figure 22.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.10.6 Auto-Erase Mode AC Characteristics Table 22.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Notes on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) FA17 to FA0 CE tnxtc tce OE WE tnxtc twep tf tf tr toe tdf tr tds tds FO7 to FO0 tceh tces tceh tces tnxtc twep tdh tdh H'71 H'71 Data Note: FO2 and FO3 are undefined. Figure 22.22 Status Read Mode Timing Waveforms Table 22.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Table 22.20 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 22.10.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) 22.10.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT) Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.1 Overview H8S/2148 F-ZTAT A-mask version and H8S/2144 F-ZTAT A-mask version have 128 kbytes, and H8S/2147 F-ZTAT A-mask version has 64 kbytes of on-chip flash memory. The flash memory is connected to the bus master by a 16-bit data bus.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.1.2 Register Configuration This group on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 23.1. Table 23.1 ROM Register Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined Depends on the operating mode H'FFC5 Note: * Lower 16 bits of the address. 23.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.4 Overview of Flash Memory 23.4.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.4.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.4.3 Flash Memory Operating Modes Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 23.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) On-Board Programming Modes • Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. 2.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) • User program mode 1. Initial state (1) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Differences between Boot Mode and User Program Mode Entire memory erase Boot Mode User Program Mode Yes Yes Block erase No Yes Programming control program* Program/program-verify Program/program-verify Erase/erase-verify Notes * To be provided by the user, in accordance with the recommended algorithm.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 23.3. Table 23.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.5 Register Descriptions 23.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When SWE = 1, and PSU = 1 23.5.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 23.8.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit 7 6 5 4 3 2 1 0 EBR1 — — — — — — EB9/—* EB8/—* Initial value 0 0 0 0 0 0 Read/Write — — — — — — 0 0 1 2 1 2 * * R/W R/W* * Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write 1 R/W* R/W R/W R/W R/W R/W R/W R/W EBR2 2 2 Notes: 1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate The chip measures low period of H'00 data transmitted by host The chip calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indic
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 23.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Figure 23.10. The boot program area can be used when the programming control program transferred into the RAM enters the execution state. A stack area should be set up as required. H'(FF)E080 ID code area*1 H'(FF)E088 Programming control program area*1 (2040 bytes) H'(FF)E880 Boot program area*2 (1920 bytes) H'(FF)EFFF H'(FF)FF00 H'(FF)FF7F Boot program area*2 (128 bytes) Notes: 1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing an on-board means of supplying programming data, and storing a program/erase control program in part of the program area as necessary.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) program setting so that the time for one programming operation is within the range of (z1), (z2) or (z3) µs. 23.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Write pulse application subroutine Sub-routine write pulse Start of programming Start Enable WDT Set SWE bit in FLMCR1 Set PSU bit in FLMCR1 Wait (y) µs Wait (x) µs *6 Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 23.13. The wait times (x, y, z, α, β, γ, ε, η, θ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erase (N), see section 26.2.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Start *1 Set SWE bit in FLMCR1 Wait (x) µs *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *5 Clear ESU bit in FLMCR2 Wait (β) µs *5 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *5 Set block start address to verify address H'FF dummy write to verify add
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 23.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.9 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes — Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection 23.8.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Normal operation mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence*2 RES = 0 or STBY = 0 Error occurrence*1 RES = 0 or STBY = 0 Software standby, sleep, subsleep, and watch mode Error protection mode RD VF*4 PR ER FLER = 1 Legend: RD: Memory read possible VF: Verify-read possible PR
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased 1 (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation. There are three reasons for this: 1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.10 Flash Memory Programmer Mode 23.10.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 128kbyte or 64-kbyte on-chip flash memory*. See section 23.10.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.10.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory (VPP = 3.3 V). Figure 23.15 shows the memory map in programmer mode.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.11 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE FO0 to FO7 FA0 to FA17 Read L L H Data output Ain Output disable L H H Hi-Z X Command write 1 Chip disable* L H L Data input Ain* H X X Hi-Z X 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.13 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.14 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.15 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.10.5 Auto-Program Mode AC Characteristics Table 23.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Address stable FA17 to FA0 tceh CE tas tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf tds tdh Programming normal end identification signal FO6 Programming wait FO7 to FO0 H'40 Data Data FO0 to FO5 = 0 Figure 23.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.10.6 Auto-Erase Mode AC Characteristics Table 23.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Notes on Use of Auto-Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) FA17 to FA0 CE tnxtc tce OE WE tnxtc twep tf tf tr toe tdf tr tds tds FO7 to FO0 tceh tces tceh tces tnxtc twep tdh tdh H'71 H'71 Data Note: FO2 and FO3 are undefined. Figure 23.22 Status Read Mode Timing Waveforms Table 23.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Table 23.20 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 23.10.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) 23.10.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Do not set or clear the SWE bit during program execution in flash memory. Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1 the flash memory can only be read in program-verify or erase-verify mode.
Section 24 Clock Pulse Generator Section 24 Clock Pulse Generator 24.1 Overview This LSI have a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input circuit, and waveform shaping circuit. 24.1.1 Block Diagram Figure 24.
Section 24 Clock Pulse Generator 24.1.2 Register Configuration The clock pulse generator is controlled by the standby control register (SBYCR) and low-power control register (LPWRCR). Table 24.1 shows the register configuration. Table 24.1 CPG Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'00 H'FF84 Low-power control register LPWRCR R/W H'00 H'FF85 Note: * Lower 16 bits of the address. 24.2 Register Descriptions 24.2.
Section 24 Clock Pulse Generator Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is φ/2 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 1 0 1 24.2.
Section 24 Clock Pulse Generator 24.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 24.3.1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in the example in figure 24.2. Select the damping resistance Rd according to table 24.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 24.
Section 24 Clock Pulse Generator Table 24.3 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 12 16 20 RS max (Ω Ω) 500 120 80 70 60 50 40 C0 max (pF) 7 7 7 7 7 7 7 Note on Board Design When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 24.4.
Section 24 Clock Pulse Generator 24.3.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 24.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode.
Section 24 Clock Pulse Generator External Clock The external clock signal should have the same frequency as the system clock (φ). Table 24.4 and figure 24.6 show the input conditions for the external clock. Table 24.4 External Clock Input Conditions VCC = 2.7 to 5.5 V VCC = 5.0 V ±10% Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 40 — 20 — ns Figure 24.
Section 24 Clock Pulse Generator external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state. Table 24.5 External Clock Output Settling Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output settling delay time Note: * Symbol Min Max Unit Notes * 500 — µs Figure 24.7 tDEXT tDEXT includes RES pulse width (tRESW).
Section 24 Clock Pulse Generator 24.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 24.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32 clocks. 24.
Section 24 Clock Pulse Generator tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 24.
Section 24 Clock Pulse Generator 24.9 Clock Selection Circuit This circuit selects the system clock used in the MCU. The clock signal generated in the EXTAL/XTAL pin oscillator is selected as the system clock when MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. In sub-active mode, sub-sleep mode, and watch mode, the sub-clock signal input from EXCL pin is selected as the system clock.
Section 24 Clock Pulse Generator Rev. 4.
Section 25 Power-Down State Section 25 Power-Down State 25.1 Overview In addition to the normal program execution state, this LSI have a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. This LSI has the following operating modes: 1. High-speed mode 2. Medium-speed mode 3. Subactive mode 4. Sleep mode 5. Subsleep mode 6. Watch mode 7.
Section 25 Power-Down State Table 25.
Section 25 Power-Down State Program-halted state STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high Program execution state SSBY = 0, LSON = 0 High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 Clock switching exception handling after oscillation setting time (STS2 to STS0) SLEEP instruction Any interrupt*3 SLEEP instruction External interrupt*4 SSBY = 1 P
Section 25 Power-Down State Table 25.
Section 25 Power-Down State 25.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 25.3 summarizes these registers. Table 25.
Section 25 Power-Down State Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc.
Section 25 Power-Down State Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master in high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0.
Section 25 Power-Down State Bit 7 DTON Description 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or softwar
Section 25 Power-Down State Bit 5 NESEL Description 0 Sampling at φ divided by 32 1 Sampling at φ divided by 4 (Initial value) Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE Description 0 Subclock input from EXCL pin is disabled 1 Subclock input from EXCL pin is enabled (Initial value) Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 0. 25.2.
Section 25 Power-Down State For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status Register (TCSR).
Section 25 Power-Down State 25.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ).
Section 25 Power-Down State Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 25.2 Medium-Speed Mode Transition and Clearance Timing 25.4 Sleep Mode 25.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained.
Section 25 Power-Down State 25.5 Module Stop Mode 25.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 25.4 shows MSTP bits and the corresponding on-chip supporting modules.
Section 25 Power-Down State Table 25.
Section 25 Power-Down State 25.6 Software Standby Mode 25.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
Section 25 Power-Down State Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 25.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 25.5 Oscillation Settling Time Settings 20 STS2 STS1 STS0 Standby Time MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit 0 4.1 ms 0 1 1 0 1 0 8192 states 0.41 0.51 0.65 0.8 1.0 1.3 2.0 1 16384 states 0.82 1.0 1.
Section 25 Power-Down State Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 25.3 Software Standby Mode Application Example 25.6.5 Usage Note In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output.
Section 25 Power-Down State In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Section 25 Power-Down State 25.8 Watch Mode 25.8.1 Watch Mode If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except WDT1 stop.
Section 25 Power-Down State 25.9 Subsleep Mode 25.9.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop.
Section 25 Power-Down State 25.10 Subactive Mode 25.10.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode.
Section 25 Power-Down State 25.11 Direct Transition 25.11.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, mediumspeed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Voltage of Power Supply and Operating Range The power supply voltage and operating range (shaded part) for each product are shown in table 26.1. Table 26.1 Power Supply Voltage and Operating Range (1) Product/ Power supply VCC HD64F2144 5.5 V HD64F2142R Product/ Power supply 5-V version HD64F2148 Flash Memory Programming 4.5 V 4.0 V 3-V version HD64F2148V VCC HD64F2144V 5.5 V Select 5.0 V ±0.
Section 26 Electrical Characteristics Table 26.1 Power Supply Voltage and Operating Range (2) Product/ Power supply HD64F2147N Product/ Power supply 5-V version 3-V version HD64F2147NV VCC 5.5 V VCC Select 5.0 V ±0.5 V for programming condition in PROM programmer 5.5 V Flash Memory Programming 4.5 V (F-ZTAT Products) 3.6 V Flash Memory Programming 3.0 V 2 MHz VCC1 pin 16 MHz 20 MHz fop VCC = 5.0 V ±10% (fop = 2 to 20 MHz) VCC2 pin 2 MHz VCC1 pin 10 MHz fop VCC = 3.0 V to 5.
Section 26 Electrical Characteristics Table 26.1 Power Supply Voltage and Operating Range (4) Product/ Power supply HD6432148S 5-V version (Mask ROM Products) 4-V version VCC 3-V version VCC HD6432148SW 5.5 V HD6432147S 4.5 V HD6432147SW VCC 5.5 V 4.0 V HD6432144S 3.6 V HD6432143S 2.7 V 2 MHz 20 MHz VCC1 pin 2 MHz 10 MHz fop 16 MHz 2 MHz fop fop VCC = 5.0 V ±10% VCC = 4.0 V to 5.5 V VCC = 2.7 V to 3.6 V (CIN in use VCC = 3.0 V to 3.
Section 26 Electrical Characteristics 26.2 Electrical Characteristics of H8S/2148 F-ZTAT 26.2.1 Absolute Maximum Ratings Table 26.2 lists the absolute maximum ratings. Table 26.2 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +7.0 V Input/output buffer power supply (power supply for the port A) VCCB –0.3 to +7.0 V Input voltage (except ports 6, 7, and A) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.
Section 26 Electrical Characteristics 26.2.2 DC Characteristics Table 26.3 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 26.4 and 26.5, respectively. Table 26.3 DC Characteristics (1) 1 Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC* = 5.0 V ±10%, 1 1 11 AVref* = 4.
Section 26 Electrical Characteristics Item Input low voltage Min Typ Max Unit VIL –0.3 — 0.5 V PA7 to PA0 –0.3 — 1.0 NMI, EXTAL, input pins except (1) and (3) above –0.3 — 0.8 VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA 2.5 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.6 mA — — 10.0 µA Vin = 0.5 to VCC –0.5 V STBY, NMI, MD1, MD0 — — 1.0 µA Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.
Section 26 Electrical Characteristics Item Input RES capacitance NMI (4) Symbol Min Typ Max Unit Cin — — 80 pF Test Conditions Vin = 0 V, f = 1 MHz, Ta = 25°C — — 50 pF P52, P97, P42, P86 PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 85 120 mA f = 20 MHz — 70 100 mA f = 20 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.0 mA — 0.01 5.
Section 26 Electrical Characteristics 6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
Section 26 Electrical Characteristics Table 26.3 DC Characteristics (2) 11 1 Conditions: VCC = 4.0 V to 5.5 V* , VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 11 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C* (regular 11 specifications), Ta = –40 to +85°C* (wide-range specifications) Item Symbol Min Schmitt P67 to (1) trigger input P60(KWUL = 2 6 voltage 00)* * , KIN15 to 7 8 KIN8* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 VT — — — — VCC × 0.7 V VCCB × 0.7 VT + – VT – VT 0.
Section 26 Electrical Characteristics Item Input low voltage Symbol Min RES, STBY, MD1, MD0 (3) VIL PA7 to PA0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, 4 5 8 and P52* )* * P97, P52* Output low voltage VOH 4 All output pins 5 (except RESO)* VOL Ports 1 to 3 RESO Input leakage current Test Conditions Typ Max Unit –0.3 — 0.5 V –0.3 — 1.0 V VCCB = 4.5 V to 5.5 V –0.3 — 0.8 V VCCB < 4.5 V –0.3 — 0.8 V — VCC –0.5 VCCB –0.
Section 26 Electrical Characteristics Item Input pull-up MOS current Symbol Min Typ Max Unit 50 — 300 µA 60 — 500 µA Port 6 (P6PUE = 1) 15 — 150 Ports 1 to 3 8 Ports A* , B Port 6 (P6PUE = 0) 30 — 200 µA 40 — 400 µA 10 — 110 — — 80 pF — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 70 100 mA Ports 1 to 3 8 Ports A* , B Port 6 (P6PUE = 0) –IP Port 6 (P6PUE = 1) Input RES capacitance NMI (4) Current Normal opera
Section 26 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref ≤ AVCC. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4.
Section 26 Electrical Characteristics Table 26.3 DC Characteristics (3) 11 1 Conditions: VCC = 3.0 V to 5.5 V* , VCCB = 3.0 V to 5.5 V, AVCC* = 3.0 V to 5.5 V, 1 11 AVref = 3.0 V to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C* Item Symbol Schmitt (1) P67 to trigger input P60(KWUL = 2 6 voltage 00)* * , KIN15 to 7 8 KIN8* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 VT Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 swiching)* P67 to P60 (KWUL = 10) EXTAL Unit V — + — VCC × 0.7 V VCCB × 0.
Section 26 Electrical Characteristics Item Input low voltage Min Typ Max Unit VIL –0.3 — VCC × 0.1 V –0.3 — VCCB × 0.2 V VCCB < 4.0 V 0.8 V VCCB = 4.0 V to 5.5 V VCC × 0.2 V VCC < 4.0 V 0.8 V VCC = 4.0 V to 5.5 V — VCC –0.5 VCCB –0.5 — V IOH = –200 µA — VCC –1.0 VCCB –1.0 — V IOH = –1 mA (VCC < 4.0 V, VCCB < 4.0 V) 1.0 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA (VCC < 4.0 V), IOL = 10 mA (4.0 V ≤ VCC ≤ 5.5 V) RESO — — 0.
Section 26 Electrical Characteristics Item Input pullup MOS current Test Conditions Symbol Min Typ Max Unit –IP 10 — 150 µA 30 — 250 µA 3 — 70 µA — — 80 pF — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 50 70 mA f = 10 MHz — 40 60 mA f = 10 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC +0.
Section 26 Electrical Characteristics Table 26.4 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 26 Electrical Characteristics Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.
Section 26 Electrical Characteristics This chip 2 kΩ Port Darlington pair Figure 26.1 Darlington Pair Drive Circuit (Example) This chip 600 Ω Ports 1 to 3 LED Figure 26.2 LED Drive Circuit (Example) Rev. 4.
Section 26 Electrical Characteristics Table 26.5 Bus Drive Characteristics Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Schmitt trigger input voltage – VT Min Typ Max Unit Test Conditions VCC × 0.3 — — V VCC = 3.0 V to 5.5 V — — VCC × 0.7 VCC = 3.0 V to 5.5 V VT – VT VCC × 0.05 — — VCC = 3.0 V to 5.5 V Input high voltage VIH VCC × 0.7 — VCC +0.5 Input low voltage VIL –0.5 — VCC × 0.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.6 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock Pulse Generator. Table 26.6 Clock Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.7 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 26.7 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.8 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 26.8 Bus Timing (1) (Nomal Mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × tcyc –60 ns Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × tcyc –50 ns Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × tcyc –60 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
Section 26 Electrical Characteristics Table 26.8 Bus Timing (2) (Advanced mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 V to 5.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC3 access time 3 — 2.0 × tcyc –40 — 2.0 × tcyc –55 — 2.0 × tcyc –80 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.5 × tcyc –35 — 2.5 × tcyc –50 ns Read data tACC5 access time 5 — 3.0 × tcyc –40 — 3.0 × tcyc –55 — 3.
Section 26 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 26.9 to 26.11 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 26.9 Timing of On-Chip Supporting Modules (1) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics Condition A Condition B Condition C 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 26.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 26.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 26.
Section 26 Electrical Characteristics Table 26.9 Timing of On-Chip Supporting Modules (2) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.
Section 26 Electrical Characteristics Table 26.10 Keyboard Buffer Controller Timing Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit KCLK, KD output tKBF fall time 20 + 0.
Section 26 Electrical Characteristics 2 Table 26.11 I C Bus Timing Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency Ratings Item Symbol Min Typ Max Unit SCL input cycle time tSCL 12 — — tcyc SCL input high pulse width tSCLH 3 — — tcyc SCL input low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.
Section 26 Electrical Characteristics 26.2.4 A/D Conversion Characteristics Tables 26.12 and 26.13 list the A/D conversion characteristics. Table 26.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.13 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.2.5 D/A Conversion Characteristics Table 26.14 lists the D/A conversion characteristics. Table 26.14 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.2.6 Flash Memory Characteristics Table 26.15 shows the flash memory characteristics. Table 26.15 Flash Memory Characteristics (Programming/erasing operating range) Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications) (3 V version): VCC = 3.0 V to 3.
Section 26 Electrical Characteristics 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP(max) = wait time after P-bit setting (z) × maximum programming count (N) 5. Number of times when the wait time after P-bit setting (z) = 200 µs. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP(max)). 6.
Section 26 Electrical Characteristics VCC power supply External capacitor for stabilizing power supply VCL 0.47 µF one or two connected in group VSS Product incorporating internal step-down circuit For products incorporating an internal step-down circuit, do not connect the VCL pin to the VCC power supply. (The VCC1 pin must be connected to the VCC power supply as usual.) The power supply stabilization capacitor must be connected to the VCL pin. Use a monolithic ceramic capacitor of 0.
Section 26 Electrical Characteristics 26.3 Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version), H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of H8S/2148 and H8S/2147 26.3.1 Absolute Maximum Ratings Table 26.16 lists the absolute maximum ratings. Table 26.16 Absolute Maximum Ratings Item Symbol Value Unit 1 Power supply voltage* VCC –0.3 to +7.
Section 26 Electrical Characteristics Item Symbol Value Unit Operating temperature (flash memory programming/erasing) Topr Regular specifications: –20 to +75 °C Wide-range specifications: –40 to +85 °C Storage temperature Tstg –55 to +125 °C Caution: 1. Permanent damage to the chip may result if absolute maximum ratings are exceeded. 2. Never apply more than 7.0 V to any of the pins of the 5- or 4-V version or 4.3 V to any of the pins (except port A) of the 3-V version Notes: 1.
Section 26 Electrical Characteristics 26.3.2 DC Characteristics Table 26.17 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 26.18 and 26.19, respectively. Table 26.17 DC Characteristics (1) 1 Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC* = 5.0 V ±10%, 1 1 AVref* = 4.
Section 26 Electrical Characteristics Item Input low voltage Symbol Min Typ Max Unit VIL –0.3 — 0.5 V PA7 to PA0 –0.3 — 1.0 NMI, EXTAL, input pins except (1) and (3) above –0.3 — 0.8 RES, STBY, MD1, MD0 (3) — VCC –0.5 VCCB –0.5 — V IOH = –200 µA 3.5 — — V IOH = –1 mA 2.0 — — V IOH = –200 µA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.6 mA Vin = 0.5 to VCC –0.
Section 26 Electrical Characteristics Item Input RES capacitance NMI (4) Symbol Min Typ Max Unit Cin — — 80 pF Test Conditions Vin = 0 V, f = 1 MHz, Ta = 25°C — — 50 pF P52, P97, P42, P86 PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 55 70 mA f = 20 MHz — 36 55 mA f = 20 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
Section 26 Electrical Characteristics Table 26.17 DC Characteristics (2) 1 Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, 1 1 AVref* = 4.0 V to AVCC, VSS = AVSS* = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Schmitt P67 to (1) trigger input P60(KWUL = 2 6 voltage 00)* * , KIN15 to 7 8 KIN8* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 VT Typ Max Unit – 1.0 — — V + — — VCC × 0.7 V VT VCCB × 0.
Section 26 Electrical Characteristics Item Input low voltage Symbol Min Max Unit –0.3 — 0.5 V –0.3 — 1.0 V VCCB = 4.5 V to 5.5 V –0.3 — 0.8 V VCCB = 4.0 V to 4.5 V –0.3 — 0.8 V — VCC –0.5 VCCB –0.5 — V IOH = –200 µA 3.5 — — V IOH = –1 mA, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V 3.0 — — V IOH = –1 mA, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V o 4.5 V 1.5 — — V IOH = –200 µA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.
Section 26 Electrical Characteristics Item Input pull-up MOS current Symbol Min Typ Max Unit 30 — 300 µA 60 — 600 µA Port 6 (P6PUE = 1) 15 — 200 Ports 1 to 3 8 Ports A* , B Port 6 (P6PUE = 0) 20 — 200 µA 40 — 500 µA 10 — 150 — — 80 pF — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 45 58 mA Ports 1 to 3 8 Ports A* , B Port 6 (P6PUE = 0) –IP Port 6 (P6PUE = 1) Input RES capacitance NMI (4) Current Normal operat
Section 26 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref ≤ AVCC. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4.
Section 26 Electrical Characteristics Table 26.17 DC Characteristics (3) 11 1 Conditions: VCC = 2.7 V to 3.6 V* , VCCB = 2.7 V to 5.5 V, AVCC* = 2.7 V to 3.6 V, 1 AVref = 2.7 V to 3.6 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Symbol Schmitt P67 to (1) trigger input P60(KWUL = 2 6 voltage 00)* * , KIN15 to 7 8 KIN8* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 VT Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 swiching)* P67 to P60 (KWUL = 10) Unit V — + — VCC × 0.7 V VCCB × 0.
Section 26 Electrical Characteristics Item Input low voltage Min Typ Max Unit VIL –0.3 — VCC × 0.1 V –0.3 — VCCB × 0.2 V VCCB = 2.7 V to 4.0 V 0.8 V VCCB = 4.0 V to 5.5 V VCC × 0.2 V VCC = 2.7 V to 3.6 V — VCC –0.5 VCCB –0.5 — V IOH = –200 µA VCC –1.0 — VCCB –1.0 — V IOH = –1 mA (VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 4.0 V) 0.5 — — V IOH = –200 µA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA RESO — — 0.4 V IOL = 1.6 mA — — 10.
Section 26 Electrical Characteristics Item Input pullup MOS current Test Conditions Symbol Min Typ Max Unit –IP 5 — 150 µA 30 — 300 µA 3 — 100 µA — — 80 pF NMI — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 30 40 mA f = 10 MHz — 20 32 mA f = 10 MHz — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC +0.
Section 26 Electrical Characteristics Table 26.18 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 26 Electrical Characteristics Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.
Section 26 Electrical Characteristics Table 26.19 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Schmitt trigger input voltage – VT Min Typ Max Unit VCC × 0.3 — — V Test Conditions — — VCC × 0.7 VT – VT VCC × 0.05 — — Input high voltage VIH VCC × 0.7 — VCC +0.5 Input low voltage VIL –0.5 — VCC × 0.3 Output low voltage VOL — — 0.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.20 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock Pulse Generator. Table 26.20 Clock Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.21 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 26.21 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.22 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 26.22 Bus Timing (1) (Nomal mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × tcyc –60 ns Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × tcyc –50 ns Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × tcyc –60 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
Section 26 Electrical Characteristics Table 26.22 Bus Timing (2) (Advanced mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 2.7 V to 3.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC3 access time 3 — 2.0 × tcyc –40 — 2.0 × tcyc –55 — 2.0 × tcyc –80 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.5 × tcyc –35 — 2.5 × tcyc –50 ns Read data tACC5 access time 5 — 3.0 × tcyc –40 — 3.0 × tcyc –55 — 3.
Section 26 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 26.23 to 26.25 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 26.23 Timing of On-Chip Supporting Modules (1) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics Condition A Condition B Condition C 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 26.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 26.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 26.
Section 26 Electrical Characteristics Table 26.23 Timing of On-Chip Supporting Modules (2) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 2.
Section 26 Electrical Characteristics Table 26.24 Keyboard Buffer Controller Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit KCLK, KD output tKBF fall time 20 + 0.
Section 26 Electrical Characteristics 2 Table 26.25 I C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V, φ = 5 MHz to maximum operating frequency Ratings Item Symbol Min Typ Max Unit SCL input cycle time tSCL 12 — — tcyc SCL input high pulse width tSCLH 3 — — tcyc SCL input low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.5* tcyc SCL, SDA input fall time tSf — — 300 ns SCL, SDA output tof fall time 20 + 0.
Section 26 Electrical Characteristics 26.3.4 A/D Conversion Characteristics Tables 26.26 and 26.27 list the A/D conversion characteristics. Table 26.26 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.27 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.3.5 D/A Conversion Characteristics Table 26.28 lists the D/A conversion characteristics. Table 26.28 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics Table 26.29 Flash Memory Characteristics (Programming/erasing operating range) Conditions (5 V version): VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) (3 V version): VCC = 3.0 V to 3.
Section 26 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Section 26 Electrical Characteristics 26.3.7 Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
Section 26 Electrical Characteristics 26.4 Electrical Characteristics of H8S/2147N F-ZTAT 26.4.1 Absolute Maximum Ratings Table 26.30 lists the absolute maximum ratings. Table 26.30 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +7.0 V Input/output buffer power supply (power supply for the port A) VCCB –0.3 to +7.0 V Input voltage (except ports 6, 7, and A) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.
Section 26 Electrical Characteristics 26.4.2 DC Characteristics Table 26.31 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 26.32 and 26.33, respectively. Table 26.31 DC Characteristics (1) 1 Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC* = 5.0 V ±10%, 1 1 11 AVref* = 4.
Section 26 Electrical Characteristics Item Input low voltage Min Typ Max Unit VIL –0.3 — 0.5 V PA7 to PA0 –0.3 — 1.0 NMI, EXTAL, input pins except (1) and (3) above –0.3 — 0.8 VCC –0.5 — — V IOH = –200 µA 3.5 — — V IOH = –1 mA 2.5 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.6 mA Vin = 0.5 to VCC –0.
Section 26 Electrical Characteristics Item Input RES capacitance NMI (4) Symbol Min Typ Max Unit Cin — — 80 pF Test Conditions Vin = 0 V, f = 1 MHz, Ta = 25°C — — 50 pF P52, P97, P42, P86 PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 75 100 mA f = 20 MHz — 60 85 mA f = 20 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
Section 26 Electrical Characteristics Table 26.31 DC Characteristics (2) 11 1 Conditions: VCC = 3.0 V to 5.5 V* , VCCB = 3.0 V to 5.5 V, AVCC* = 3.0 V to 5.5 V, 1 11 AVref = 3.0 V to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C* Item Symbol Schmitt P67 to (1) trigger input P60(KWUL = 2 6 voltage 00)* * , KIN15 to 7 8 KIN8* * , 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 VT Schmitt P67 to P60 trigger input (KWUL = 01) voltage (in level 6 swiching)* P67 to P60 (KWUL = 10) EXTAL Unit V — + — VCC × 0.
Section 26 Electrical Characteristics Item Input low voltage Min Typ Max Unit VIL –0.3 — VCC × 0.1 V –0.3 — VCCB × 0.2 V VCCB = 3.0 V to 4.0 V 0.8 V VCCB = 4.0 V to 5.5 V VCC × 0.2 V VCC = 3.0 V to 4.0 V 0.8 V VCC = 4.0 V to 5.5 V — VCC –0.5 VCCB –0.5 — V IOH = –200 µA — VCC –1.0 VCCB –1.0 — V IOH = –1 mA (VCC = 3.0 V to 4.0 V, VCCB = 3.0 V to 4.0 V) 1.0 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA (VCC < 4.0 V), IOL = 10 mA (4.
Section 26 Electrical Characteristics Item Input pullup MOS current Test Conditions Symbol Min Typ Max Unit –IP 10 — 150 µA 30 — 250 µA 3 — 70 µA — — 80 pF — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 45 60 mA f = 10 MHz — 35 50 mA f = 10 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 4. In the H8S/2147N, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). In the H8S/2147N, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC +0.
Section 26 Electrical Characteristics Table 26.32 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.
Section 26 Electrical Characteristics Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.
Section 26 Electrical Characteristics Table 26.33 Bus Drive Characteristics Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Schmitt trigger input voltage – VT Min Typ Max Unit Test Conditions VCC × 0.3 — — V VCC = 3.0 V to 5.5 V — — VCC × 0.7 VCC = 3.0 V to 5.5 V VT – VT VCC × 0.05 — — VCC = 3.0 V to 5.5 V Input high voltage VIH VCC × 0.7 — VCC +0.5 Input low voltage VIL –0.5 — VCC × 0.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.34 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock Pulse Generator. Table 26.34 Clock Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.35 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 26.35 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.36 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 26.36 Bus Timing (1) (Nomal mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.
Section 26 Electrical Characteristics Item Symbol Condition A Condition B 20 MHz 10 MHz Min Max Min Max Unit Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –60 ns Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –50 ns Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –60 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.5 × tcyc –50 ns Read data tACC5 access time 5 — 3.0 × tcyc –30 — 3.
Section 26 Electrical Characteristics Table 26.36 Bus Timing (2) (Advanced mode) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Item Symbol Condition A Condition B 20 MHz 10 MHz Min Max Min Max Unit Address tAD delay time — 30 — 60 ns Address tAS setup time 0.5 × tcyc –25 — 0.
Section 26 Electrical Characteristics Item Symbol Condition A Condition B 20 MHz 10 MHz Min Max Min Max Unit Read data tACC3 access time 3 — 2.0 × tcyc –40 — 2.0 × tcyc –80 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.5 × tcyc –50 ns Read data tACC5 access time 5 — 3.0 × tcyc –40 — 3.0 × tcyc –80 ns WR delay time 1 tWRD1 — 30 — 60 ns WR delay time 2 tWRD2 — 30 — 60 ns WR pulse width 1 tWSW1 1.0 × tcyc –20 — 1.
Section 26 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 26.37 to 26.39 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 26.37 Timing of On-Chip Supporting Modules (1) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics Item TMR Condition B 20 MHz 10 MHz Test Conditions Symbol Min Max Min Max Unit Timer output delay time tTMOD — 50 — 100 ns Timer reset input setup time tTMRS 30 — 50 — Figure 26.20 Timer clock input setup time tTMCS 30 — 50 — Figure 26.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — tPWOD — 50 — 100 ns Figure 26.21 Asynchro- tScyc nous 4 — 4 — tcyc Figure 26.
Section 26 Electrical Characteristics Table 26.37 Timing of On-Chip Supporting Modules (2) Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.
Section 26 Electrical Characteristics Table 26.38 Keyboard Buffer Controller Timing Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit KCLK, KD output tKBF fall time 20 + 0.
Section 26 Electrical Characteristics 2 Table 26.39 I C Bus Timing Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency Ratings Item Symbol Min Typ Max Unit SCL input cycle time tSCL 12 — — tcyc SCL input high pulse width tSCLH 3 — — tcyc SCL input low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.
Section 26 Electrical Characteristics 26.4.4 A/D Conversion Characteristics Tables 26.40 and 26.41 list the A/D conversion characteristics. Table 26.40 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.
Section 26 Electrical Characteristics Table 26.41 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.
Section 26 Electrical Characteristics 26.4.5 D/A Conversion Characteristics Table 26.42 lists the D/A conversion characteristics. Table 26.42 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.
Section 26 Electrical Characteristics 26.4.6 Flash Memory Characteristics Table 26.43 shows the flash memory characteristics. Table 26.43 Flash Memory Characteristics (Programming/erasing operating range) Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (3 V version): VCC = 3.0 V to 3.
Section 26 Electrical Characteristics 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP(max) = wait time after P-bit setting (z) × maximum programming count (N) 5. Number of times when the wait time after P-bit setting (z) = 200 µs. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP(max)). 6.
Section 26 Electrical Characteristics 26.5 Electrical Characteristics of H8S/2144 F-ZTAT, H8S/2142 F-ZTAT, and Mask ROM Version of H8S/2142 26.5.1 Absolute Maximum Ratings Table 26.44 lists the absolute maximum ratings. Table 26.44 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +7.0 V Input voltage (except ports 6, 7, and A) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6 and A) Vin –0.3 to VCC +0.
Section 26 Electrical Characteristics 26.5.2 DC Characteristics Table 26.45 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 26.46 and 26.47, respectively. Table 26.45 DC Characteristics (1) 1 1 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.0 V ±10%, AVref* = 4.
Section 26 Electrical Characteristics Item Input leakage current Test Conditions Symbol Min Typ Max Unit Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V RES Vin = 0.5 to VCC –0.5 V Three-state Ports 1 to 6, 8, leakage 9, A, B current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.
Section 26 Electrical Characteristics Item Symbol Min Typ Max Unit Test Conditions 1 Analog power supply voltage* AVCC 4.5 — 5.5 V Operating Idle/not used RAM standby voltage VRAM 2.0 — 5.5 V 2.0 — — V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.
Section 26 Electrical Characteristics Table 26.45 DC Characteristics (2) 8 1 1 Conditions: VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, AVref* = 4.0 V to AVCC, 1 8 VSS = AVSS* = 0 V, Ta = –20 to +75°C* (regular specifications), 8 Ta = –40 to +85°C* (wide-range specifications) Item Symbol Min 2 5 Schmitt P67 to P60* * , (1) 5 trigger input KIN15 to KIN8* , 3 * voltage IRQ2 to IRQ0 , IRQ5 to IRQ3 VT – + VT + – VT – VT Unit 1.0 — — V — — VCC × 0.7 V V Test Conditions VCC = 4.5 V to 5.
Section 26 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOL — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.6 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V Item Output low voltage Input leakage current All output pins 4 (except RESO)* RES Iin Three-state Ports 1 to 6, 8, leakage 9, A, B current (off state) ITSI — — 1.0 µA Vin = 0.
Section 26 Electrical Characteristics Item Reference power supply current Symbol Min Typ Max Unit Test Conditions During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 mA Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 4.0 — 5.5 V Operating 2.0 — 5.5 V Idle/not used 2.0 — — V Analog power supply voltage* RAM standby voltage 1 AVCC VRAM Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used.
Section 26 Electrical Characteristics Table 26.45 DC Characteristics (3) 1 1 Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC* = 2.7 V to 5.5 V, AVref* = 2.7 V 1 to 5.5 V, VSS = AVSS* = 0 V, Ta = –20 to +75°C 8 1 (Flash memory version): VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, AVref = 3.0 V 1 8 to 5.
Section 26 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOL — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA (VCC < 4.0 V), IOL = 10 mA (4.0 V ≤ VCC ≤ 5.5 V) RESO — — 0.4 V IOL = 1.6 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.
Section 26 Electrical Characteristics Item Reference power supply current Symbol Test Conditions Min Typ Max Unit During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 mA Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 2.7 — 5.5 V Operating (mask ROM version) 3.0 — 5.5 V Operating (F-ZTAT version) 2.0 — 5.5 V Idle/not used 2.0 — — V 1 Analog power supply voltage* RAM standby voltage AVCC VRAM Notes: 1.
Section 26 Electrical Characteristics Table 26.46 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.47 Bus Drive Characteristics Conditions: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version), VSS = 0 V Applicable Pins: PA7 to PA4 (bus drive function selected) Item Symbol Min Typ Max Unit Test Conditions Output low voltage VOL — — 0.8 V IOL = 16 mA, VCC = 4.5 V to 5.5 V — — 0.5 IOL = 8 mA — — 0.4 IOL = 3 mA 26.5.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.48 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock Pulse Generator. Table 26.48 Clock Timing Condition A: VCC = 5.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.49 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 26.49 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (widerange specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.50 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 26.50 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × tcyc –60 ns Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × tcyc –50 ns Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × tcyc –60 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
Section 26 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 26.51 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 26.51 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics Condition A Condition B Condition C 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 26.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 26.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 26.
Section 26 Electrical Characteristics 26.5.4 A/D Conversion Characteristics Tables 26.52 and 26.53 list the A/D conversion characteristics. Table 26.52 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.53 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.5.5 D/A Conversion Characteristics Table 26.54 lists the D/A conversion characteristics. Table 26.54 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.5.6 Flash Memory Characteristics Table 26.55 shows the flash memory characteristics. Table 26.55 Flash Memory Characteristics (Programming/erasing operating range) Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications) (3 V version): VCC = 3.0 V to 3.
Section 26 Electrical Characteristics 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = wait time after P-bit setting (z) × maximum programming count (N) 5. Number of times when the wait time after P-bit setting (z) = 200 µs. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP (max)). 6.
Section 26 Electrical Characteristics 26.6 Electrical Characteristics of H8S/2144 F-ZTAT (A-mask version) and Mask ROM Versions of H8S/2144 and H8S/2143 26.6.1 Absolute Maximum Ratings Table 26.56 lists the absolute maximum ratings. Table 26.56 Absolute Maximum Ratings Item Symbol Value Unit 1 Power supply voltage* 1 Power supply voltage* (3-V version) VCC –0.3 to +7.0 V VCC –0.3 to +4.3 V Power supply voltage* (VCL pin) VCL –0.3 to +4.
Section 26 Electrical Characteristics 26.6.2 DC Characteristics Table 26.57 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 26.58 and 26.59, respectively. Table 26.57 DC Characteristics (1) 1 1 Conditions: VCC = 5.0 V ±10%, AVCC* = 5.0 V ±10%, AVref* = 4.
Section 26 Electrical Characteristics Item Input leakage current Test Conditions Symbol Min Typ Max Unit Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V RES Vin = 0.5 to VCC –0.5 V Three-state Ports 1 to 6, 8, leakage 9, A, B current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.
Section 26 Electrical Characteristics Item Symbol Min Typ Max Unit Test Conditions 1 Analog power supply voltage* AVCC 4.5 — 5.5 V Operating Idle/not used RAM standby voltage VRAM 2.0 — 5.5 V 2.0 — — V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.
Section 26 Electrical Characteristics Table 26.57 DC Characteristics (2) 1 1 Conditions: VCC = 4.0 V to 5.5 V, AVCC* = 4.0 V to 5.5 V, AVref* = 4.0 V to AVCC, 1 VSS = AVSS* = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min 2 5 Schmitt P67 to P60* * , (1) 5 trigger input KIN15 to KIN8* , 3 * voltage IRQ2 to IRQ0 , IRQ5 to IRQ3 VT – + VT + – VT – VT Unit 1.0 — — V — — VCC × 0.7 V 0.4 — — V Test Conditions VCC = 4.5 V to 5.
Section 26 Electrical Characteristics Symbol Min Typ Max Unit Test Conditions VOL — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 10 mA RESO — — 0.4 V IOL = 2.6 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC –0.5 V Port 7 — — 1.0 µA Vin = 0.5 to AVCC –0.5 V Item Output low voltage Input leakage current All output pins 4 (except RESO)* RES Iin Three-state Ports 1 to 6, 8, leakage 9, A, B current (off state) ITSI — — 1.0 µA Vin = 0.
Section 26 Electrical Characteristics Item Reference power supply current Symbol Min Typ Max Unit Test Conditions During A/D conversion Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 mA Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 4.0 — 5.5 V Operating 2.0 — 5.5 V Idle/not used 2.0 — — V 1 Analog power supply voltage* RAM standby voltage AVCC VRAM Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used.
Section 26 Electrical Characteristics Table 26.57 DC Characteristics (3) 8 1 1 Conditions: VCC = 2.7 V to 3.6 V* , AVCC* = 2.7 V to 3.6 V, AVref* = 2.7 V to 3.6 V, 1 VSS = AVSS* = 0 V, Ta = –20 to +75°C Item Symbol 2 5 Schmitt P67 to P60* * , (1) 5 trigger input KIN15 to KIN8* , 3 IRQ2 to IRQ0* , voltage IRQ5 to IRQ3 VT Input high voltage Input low voltage – + VT Max Unit VCC × 0.2 — — V — — VCC × 0.7 V Test Conditions VCC × 0.05 — — V VIH VCC × 0.9 — VCC +0.
Section 26 Electrical Characteristics Test Conditions Item Symbol Min Typ Max Unit Three-state Ports 1 to 6, 8, leakage 9, A, B current (off state) ITSI — — 1.0 µA Vin = 0.5 to VCC –0.5 V Input pullup MOS current –IP 5 — 150 µA 30 — 300 µA Vin = 0 V, VCC = 2.7 V to 3.6 V — — 80 pF — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above — — 15 pF — 30 40 mA — 20 32 mA — 1.0 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.
Section 26 Electrical Characteristics 4. When IICS = 0. Low-level output when the bus drive function is selected is determined separately. 5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 6. Current dissipation values are for VIH min = VCC –0.2 V, and VIL max = 0.
Section 26 Electrical Characteristics Table 26.58 Permissible Output Currents Conditions: VCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.59 Bus Drive Characteristics Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V Applicable Pins: PA7 to PA4 (bus drive function selected) Item Symbol Min Typ Max Unit Test Conditions Output low voltage VOL — — 0.8 V IOL = 16 mA, VCC = 4.5 V to 5.5 V — — 0.5 IOL = 8 mA — — 0.4 IOL = 3 mA 26.6.
Section 26 Electrical Characteristics (1) Clock Timing Table 26.60 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock Pulse Generator. Table 26.60 Clock Timing Condition A: VCC = 5.
Section 26 Electrical Characteristics (2) Control Signal Timing Table 26.61 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 26.61 Control Signal Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (widerange specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics (3) Bus Timing Table 26.62 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (φ = 32.768 kHz). Table 26.62 Bus Timing Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.
Section 26 Electrical Characteristics Item Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Symbol Min Max Min Max Min Max Test Unit Conditions Read data tACC1 access time 1 — 1.0 × tcyc –30 — 1.0 × tcyc –40 — 1.0 × tcyc –60 ns Read data tACC2 access time 2 — 1.5 × tcyc –25 — 1.5 × tcyc –35 — 1.5 × tcyc –50 ns Read data tACC3 access time 3 — 2.0 × tcyc –30 — 2.0 × tcyc –40 — 2.0 × tcyc –60 ns Read data tACC4 access time 4 — 2.5 × tcyc –25 — 2.
Section 26 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Tables 26.63 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 26.63 Timing of On-Chip Supporting Modules Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.
Section 26 Electrical Characteristics Condition A Condition B Condition C 20 MHz Max Min Max Min Max Test Unit Conditions Timer output delay time tTMOD — 50 — 50 — 100 ns Timer reset input setup time tTMRS 30 — 30 — 50 — Figure 26.20 Timer clock input setup time tTMCS 30 — 30 — 50 — Figure 26.19 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — 2.5 — tPWOD — 50 — 50 — 100 ns Figure 26.
Section 26 Electrical Characteristics 26.6.4 A/D Conversion Characteristics Tables 26.64 and 26.65 list the A/D conversion characteristics. Table 26.64 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.
Section 26 Electrical Characteristics Table 26.65 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics 26.6.5 D/A Conversion Characteristics Table 26.66 lists the D/A conversion characteristics. Table 26.66 D/A Conversion Characteristics Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.
Section 26 Electrical Characteristics Table 26.67 Flash Memory Characteristics (Programming/erasing operating range) Conditions (5 V version): VCC = 4.0 V to 5.5 V,VSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) (3 V version): VCC = 3.0 V to 3.
Section 26 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Section 26 Electrical Characteristics 26.6.7 Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc.
Section 26 Electrical Characteristics 26.7 Operational Timing 26.7.1 Test Conditions for the AC Characteristics VCC RL C = 30 pF: All output ports RL = 2.4 kΩ RH = 12 kΩ Chip output pin I/O timing test levels • Low level: 0.8 V • High level: 2.0 V RH C Figure 26.4 Output Load Circuit 26.7.2 Clock Timing tcyc tCH tCf φ tCL tCr Figure 26.5 System Clock Timing Rev. 4.
Section 26 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 26.6 Oscillation Settling Timing 26.7.3 Control Signal Timing φ NMI IRQi (i = 0, 1, 2, 6, 7) tOSC2 Figure 26.7 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 4.
Section 26 Electrical Characteristics φ tRESS tRESS RES tRESW Figure 26.8 Reset Input Timing φ tNMIH tNMIS NMI tNMIW IRQi (i = 7 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 26.9 Interrupt Input Timing Rev. 4.
Section 26 Electrical Characteristics 26.7.4 Bus Timing T1 T2 φ tAD A23 to A0, IOS* tCSD tAH tAS tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 26.10 Basic Bus Timing (Two-State Access) Rev. 4.
Section 26 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0, IOS* tCSD tAS tASD tAH tASD AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 26.11 Basic Bus Timing (Three-State Access) Rev. 4.
Section 26 Electrical Characteristics T1 T2 TW T3 φ A23 to A0, IOS* AS* RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 26.12 Basic Bus Timing (Three-State Access with One Wait State) Rev. 4.
Section 26 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 26.13 Burst ROM Access Timing (Two-State Access) Rev. 4.
Section 26 Electrical Characteristics T1 T2 or T3 T1 φ tAD A23 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 26.14 Burst ROM Access Timing (One-State Access) Rev. 4.
Section 26 Electrical Characteristics 26.7.5 Timing of On-Chip Supporting Modules T1 T2 φ tPRS tPRH Ports 1 to 9, A, B (read) tPWD Ports 1 to 6, 8, 9, A, B (write) Figure 26.15 I/O Port Input/Output Timing φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 26.16 FRT Input/Output Timing φ tFTCS FTCI tFTCWL tFTCWH Figure 26.17 FRT Clock Input Timing Rev. 4.
Section 26 Electrical Characteristics φ tTMOD TMO0, TMO1 TMOX Figure 26.18 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 26.19 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 26.20 8-Bit Timer Reset Input Timing φ tPWOD PW15 to PW0, PWX1 to PWX0 Figure 26.21 PWM, PWMX Output Timing Rev. 4.
Section 26 Electrical Characteristics tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 26.22 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 26.23 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 26.24 A/D Converter External Trigger Input Timing φ tRESD tRESD RESO tRESOW Figure 26.25 WDT Output Timing (RESO RESO) RESO Rev. 4.
Section 26 Electrical Characteristics Host interface read timing CS/HA0 tHAR tHRPW tHRA IOR tHRD HDB7 to HDB0 tHRF Valid data tHIRQ HIRQi* (i = 1, 3, 4, 11, 12) Note: * The rising edge timing is the same as the port 4 and port B output timing. See figure 26.15. Host interface write timing CS/HA0 tHAW tHWPW tHWA IOW tHDW tHWD HDB7 to HDB0 tHGA GA20 Figure 26.26 Host Interface Timing Rev. 4.
Section 26 Electrical Characteristics 1. Reception φ tKBIS tKBIH KCLK/ KD* 2. Transmission (a) T1 T2 φ tKBOD KCLK/ KD* Transmission (b) KCLK/ KD* tKBF Note: φ shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. * KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Figure 26.27 Keyboard Buffer Controller Timing Rev. 4.
Section 26 Electrical Characteristics VIH SDA0, SDA1 VIL tBUF tSCLH tSTAH SCL0, SCL1 P* tSTAS S* tSf tof tSP tSTOS Sr* tSCLL tSr tSCL P* tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 26.28 I C Bus Interface Input/Output Timing (Option) Rev. 4.
Appendix A Instruction Set Appendix A Instruction Set A.
Appendix A Instruction Set Condition Code Notation Symbol Meaning Changes according operation result. * Indeterminate (value not guaranteed). 0 Always cleared to 0. 1 Always set to 1. — Not affected by operation result. Rev. 4.
Appendix A Instruction Set Table A.1 Instruction Set 1. Data Transfer Instructions B MOV.B @ERs+,Rd B MOV.B @aa:8,Rd B MOV.B @aa:16,Rd H N Z V C Advanced MOV.B @(d:32,ERs),Rd No. of States*1 Normal B I — MOV.B @(d:16,ERs),Rd @@aa B @(d,PC) MOV.B @ERs,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B MOV.B Rs,Rd @ERn MOV.
Appendix A Instruction Set L MOV.L @ERs+,ERd L MOV.L @aa:16,ERd L MOV.L @aa:32,ERd L MOV.L ERs,@ERd L MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd L MOV.L ERs,@aa:16 L MOV.L ERs,@aa:32 L POP.W Rn W POP.L ERn H N Z V C Advanced MOV.L @(d:32,ERs),ERd No. of States*1 Normal L I — MOV.L @(d:16,ERs),ERd @@aa L @(d,PC) MOV.L @ERs,ERd Condition Code Operation @aa 6 L @-ERn/@ERn+ L MOV.L ERs,ERd @ERn MOV.
Appendix A Instruction Set 2. Arithmetic Instructions L ADD.L ERs,ERd L ADDX #xx:8,Rd B ADDX Rs,Rd B ADDS #1,ERd H N Z V C Advanced ADD.L #xx:32,ERd No. of States*1 Normal W I — ADD.W Rs,Rd @@aa W @(d,PC) ADD.W #xx:16,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B ADD.B Rs,Rd @ERn ADD.
Appendix A Instruction Set Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) DAS DAS Rd B 2 Rd8 decimal adjust →Rd8 — * * — 1 MULXU MULXU.B Rs,Rd B 2 Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — 12 MULXU.W Rs,ERd W 2 Rd16×Rs16→ERd32 (unsigned multiplication) — — — — — — 20 MULXS.
Appendix A Instruction Set MAC MAC @ERn+,@ERm+ Condition Code No. of States*1 Cannot be used with this LSI. V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) [2] CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Rev. 4.
Appendix A Instruction Set 3. Logic Instructions OR XOR NOT L AND.L ERs,ERd L OR.B #xx:8,Rd B OR.B Rs,Rd B OR.W #xx:16,Rd W OR.W Rs,Rd W OR.L #xx:32,ERd L OR.L ERs,ERd L XOR.B #xx:8,Rd B XOR.B Rs,Rd B XOR.W #xx:16,Rd W XOR.W Rs,Rd W XOR.L #xx:32,ERd L XOR.L ERs,ERd L NOT.B Rd H N Z V C Advanced AND.L #xx:32,ERd No. of States*1 Normal W I — AND.W Rs,Rd @@aa W @(d,PC) AND.W #xx:16,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B AND.B Rs,Rd @ERn AND.
Appendix A Instruction Set 4. Shift Instructions SHAL SHAR SHLL SHLR ROTXL Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) SHAL.B Rd B 2 — — 1 SHAL.B #2,Rd B 2 — — 1 SHAL.W Rd W 2 0 — — 1 SHAL.W #2,Rd W 2 — — 1 SHAL.L ERd L 2 — — 1 SHAL.L #2,ERd L 2 — — SHAR.B Rd B 2 — — 0 1 SHAR.B #2,Rd B 2 — — 0 1 SHAR.
Appendix A Instruction Set ROTXR ROTL ROTR Condition Code No. of States*1 V C Advanced H N Z Normal I — @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) ROTXR.B Rd B 2 — — 0 1 ROTXR.B #2,Rd B 2 — — 0 1 ROTXR.W Rd W 2 — — 0 1 ROTXR.W #2,Rd W 2 — — 0 1 ROTXR.L ERd L 2 — — 0 1 ROTXR.L #2,ERd L 2 — — 0 1 ROTL.B Rd B 2 — — 0 1 ROTL.B #2,Rd B 2 — — 0 1 ROTL.
Appendix A Instruction Set 5. Bit-Manipulation Instructions BSET BCLR BNOT Condition Code No.
Appendix A Instruction Set BTST BLD BILD BST BIST Condition Code No.
Appendix A Instruction Set BAND BIAND BOR BIOR BXOR BIXOR Condition Code No.
Appendix A Instruction Set 6. Branch Instructions Bcc H N Z V C Advanced I — @@aa @(d,PC) Branch Condition No.
Appendix A Instruction Set JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — Condition Code No.
Appendix A Instruction Set 7. System Control Instructions Condition Code No.
Appendix A Instruction Set STC ANDC ORC XORC NOP Condition Code No.
Appendix A Instruction Set 8. Block Transfer Instructions No. of States*1 V C Normal H N Z — @@aa @(d,PC) I Advanced Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn #xx Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) EEPMOV EEPMOV.B — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; — — — — — — 4+2n*2 EEPMOV.W — 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; — — — — — — 4+2n*2 Notes: 1.
Bcc BAND ANDC AND 6 rs 6 F 9 6 A 1 6 1 7 6 7 0 0 0 W L L B B AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR 1 3 E A A 0 8 1 8 7 6 6 4 5 4 5 B B B — — — — BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 1 0 0 erd C 7 B BAND #xx:3,@ERd disp disp abs 0 IMM 6 7 IMM B rd rd rd 0 0 0 0 0 rd 1 0 0 erd IMM rd 0 erd 0 erd 0 erd IMM BAND #xx:3,Rd 4 rs 6 1 B W AND.
Bcc Instruction — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Size BHI d:8 Mnemonic Rev. 4.
BIOR BILD BIAND BCLR Instruction B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Size BCLR #xx:3,Rd Mnemonic 6
Rev. 4.
BTST BST BSR BSET BOR Instruction B B B B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@
6 6 7 7 7 6 6 B B B B B B B BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 Rev. 4.00 Sep 27, 2006 page 948 of 1130 REJ09B0327-0400 5 5 7 7 B — — EEPMOV EEPMOV.B EEPMOV.W L DEC.L #1,ERd W 1 W DEC.W #2,Rd DIVXU.W Rs,ERd 1 W DEC.W #1,Rd DIVXU.B Rs,Rd 1 B DEC.B Rd DEC 0 1 B DAS Rd DAS W 1 B DAA Rd DAA DIVXS.W Rs,ERd 0 L CMP.L ERs,ERd 0 1 L CMP.L #xx:32,ERd 1 7 W CMP.W Rs,Rd L 1 W CMP.
LDC JSR JMP INC EXTU EXTS Instruction W W W W W W W W LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR B LDC Rs,CCR W B LDC #xx:8,EXR LDC @ERs,EXR B LDC #xx:8,CCR B — JSR @@aa:8 W — JSR @aa:24 LDC @ERs,CCR — JSR @ERn LDC Rs,EXR — JMP @@aa:8 INC.L #2,ERd — L INC.L #1,ERd JMP @aa:24 L INC.W #2,Rd — W INC.W #1,Rd JMP @ERn B W INC.B Rd L EXTU.L ERd L W EXTS.L ERd EXTU.
B B B B B B B B B B B B B B B B W W W W W MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV L — MAC @ERn+,@ERm+ LDMAC ERs,MACL L LDM.L @SP+, (ERn-ERn+3) L L LDM.
0 ers 0 erd 0 erd 0 erd 0 ers 0 2 D B B 7 6 6 6 0 erd 0 0 0 0 0 0 0 0 0 0 0 0 0 B A F 1 1 1 1 1 1 6 7 0 0 0 0 0 0 0 1 erd 0 ers 0 erd 1 erd 0 ers 8 A F 8 D B B 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 L L L L L L L L L L MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L L MOV.L @ERs,ERd MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.
Rev. 4.00 Sep 27, 2006 page 952 of 1130 REJ09B0327-0400 6 7 0 0 0 6 W L L B B W OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 ROTL.B Rd ROTL.B #2, Rd 0 L B PUSH.L ERn 6 7 W OR.W #xx:16,Rd 0 1 B OR.B Rs,Rd L C B OR.B #xx:8,Rd W 1 L NOT.L ERd PUSH.W Rn 1 W NOT.W Rd POP.L ERn 1 B NOT.B Rd OR 0 — NOP 1 L NEG.L ERd NOT 1 W NEG.
rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 B W W L L SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd 1 5 — B 5 SHAL.B Rd 1 L — ROTXR.L #2, ERd SHAL 1 L ROTXR.L ERd RTS 1 W ROTXR.W #2, Rd RTS 1 W ROTXR.W Rd RTE 1 B ROTXR.B #2, Rd ROTXL.L #2, ERd 1 1 L ROTXL.L ERd 1 1 W ROTXL.
Rev. 4.00 Sep 27, 2006 page 954 of 1130 REJ09B0327-0400 6 6 6 6 7 7 6 6 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B W W STC.W EXR,@ERd STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W CCR,@ERd STC.W CCR,@(d:16,ERd) W W STC.B EXR,Rd STC.W CCR,@-ERd STC.
D 1 7 6 7 0 B B W W L L XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XOR 1 5 B B SUBX #xx:8,Rd — 1 L SUBS #4,ERd TRAPA #x:2 1 L SUBS #2,ERd TRAPA 1 L SUBS #1,ERd 0 1 L SUB.L ERs,ERd B 7 L SUB.L #xx:32,ERd B 1 W SUB.W Rs,Rd TAS @ERd*2 7 SUBX Rs,Rd 1 W SUB.W #xx:16,Rd L B SUB.
B XORC #xx:8,EXR 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Rev. 4.
1 2 BH 3 BL BHI BCLR MULXU BLS BTST DIVXU 4 5 XOR BSR BCS XOR XORC 6 AND RTE BNE AND ANDC 7 BST TRAPA BEQ SUB ADD ADD MOV OR XOR AND MOV C D E F CMP SUBX B BVS 9 Table A.3 (2) MOV Table A.3 (2) A Note: * Cannot be used with this LSI. 8 BVC MOV.B Table A.3 (2) LDC BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND OR RTS BCC OR ORC B BMI Table A.3 (2) Table A.3 (2) Table A.3 (2) Table A.3 (2) EEPMOV JMP BPL Table A.3 (2) Table A.
Rev. 4.00 Sep 27, 2006 page 958 of 1130 REJ09B0327-0400 DAS BRA MOV MOV MOV 1F 58 6A 79 7A ADD CMP CMP MOV Table A.3 (4) ADD BHI 2 SUB SUB Table A.3 (4) BLS NOT STM 3 BL 2nd byte BH BRN AL Note: * Cannot be used with this LSI.
BCLR MULXS 2 DIVXS 3 BSET 7Faa7*2 BNOT BNOT BCLR BCLR Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
Rev. 4.00 Sep 27, 2006 page 960 of 1130 REJ09B0327-0400 AH BSET 0 BNOT BNOT 1 AL 1st byte BSET 1 0 BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification.
Appendix A Instruction Set A.4 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data read/write, and other cycles occurring in each instruction, and table A.4 shows the number of states required per cycle according to the bus size.
Appendix A Instruction Set Table A.
Appendix A Instruction Set Table A.5 Number of Cycles per Instruction Instruction Mnemonic ADD Instruction Fetch I ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND.B #xx:8,Rd 1 AND.B Rs,Rd 1 AND ANDC BAND Bcc AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.L #xx:32,ERd 3 Branch Address Read J Stack Operation K Byte Data Access L AND.
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic Bcc BCLR BIAND BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE d:16 2 1 BLT d:
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I BILD 1 BIOR BIST BIXOR BLD BNOT BILD #xx:3,Rd Branch Address Read J Stack Operation K Byte Data Access L BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2 1 BIOR #xx:8,@aa:16 3 1 BIOR #xx:8,@aa:32 4 1 BIST #xx:3,Rd 1 BIST #xx:3,@ERd 2 2 BIST #xx:3,@aa:8 2 2 BIST #xx:3,@aa:16 3 2 BIST #xx:3,@aa:32 4 2
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic BOR BSET BSR BTST Stack Operation K Byte Data Access L BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 1 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #xx:3,@aa:32 4 1 BSET #xx:3,Rd 1 BSET #xx:3,@ERd 2 2 BSET #xx:3,@aa:8 2 2 BSET #xx:3,@aa:16 3 2 BSET #xx:3,@aa:32 4 2 BSET Rn,Rd 1 BSET Rn,@ERd 2 2 BSET Rn,@aa:8 2 2 BSET Rn,@aa:16 3 2 BSET Rn,@aa:32 4 2 BSR d:8 BSR d:16 BST Branch Address Read J Word Data
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I BXOR 1 BXOR #xx:3,Rd Branch Address Read J Stack Operation K Byte Data Access L BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLRMAC CLRMAC Cannot be used with this LSI. CMP CMP.B #xx:8,Rd 1 CMP.B Rs,Rd 1 CMP.W #xx:16,Rd 2 CMP.W Rs,Rd 1 CMP.L #xx:32,ERd 3 CMP.L ERs,ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC.B Rd 1 DEC.
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic JSR LDC 4 LDM* LDMAC JSR @ERn Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Normal 2 1 Advanced 2 2 JSR @aa:24 Normal 2 1 1 Advanced 2 2 1 JSR @@aa:8 Normal 2 1 1 Advanced 2 2 2 LDC #xx:8,CCR 1 LDC #xx:8,EXR 2 LDC Rs,CCR 1 LDC Rs,EXR 1 LDC @ERs,CCR 2 LDC @ERs,EXR 2 1 LDC @(d:16,ERs),CCR 3 1 LDC @(d:16,ERs),EXR 3 1 LDC @(d:32,ERs),CCR
Appendix A Instruction Set Instruction Mnemonic Instruction Fetch I MOV Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M MOV.B @aa:32,Rd 3 MOV.B Rs,@ERd 1 1 MOV.B Rs,@(d:16,ERd) 2 1 MOV.B Rs,@(d:32,ERd) 4 1 MOV.B Rs,@-ERd 1 1 MOV.B Rs,@aa:8 1 1 MOV.B Rs,@aa:16 2 1 MOV.B Rs,@aa:32 3 1 MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:32,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.
Appendix A Instruction Set Branch Address Read J Instruction Mnemonic Instruction Fetch I Cannot be used with this LSI. MOVFPE MOVFPE @:aa:16,Rd MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXS.B Rs,Rd MULXU NEG 2 19 11 MULXU.W Rs,ERd 1 19 NEG.B Rd 1 NEG.W Rd 1 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 ROTL 11 1 1 PUSH Internal Operation N MULXU.B Rs,Rd NOP POP Word Data Access M MULXS.W Rs,ERd NOP ORC Byte Data Access L 2 NEG.L ERd OR Stack Operation K OR.B #xx:8,Rd 1 OR.
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic ROTR ROTXL ROTXR ROTR.B Rd 1 ROTR.B #2,Rd 1 ROTR.W Rd 1 ROTR.W #2,Rd 1 ROTR.L ERd 1 ROTR.L #2,ERd 1 ROTXL.B Rd 1 ROTXL.B #2,Rd 1 ROTXL.W Rd 1 ROTXL.W #2,Rd 1 ROTXL.L ERd 1 ROTXL.L #2,ERd 1 ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 ROTXR.L ERd 1 ROTXR.
Appendix A Instruction Set Instruction Mnemonic SHLL SHLR Instruction Fetch I SHLL.B Rd 1 SHLL.B #2,Rd 1 SHLL.W Rd 1 SHLL.W #2,Rd 1 SHLL.L ERd 1 SHLL.L #2,ERd 1 SHLR.B Rd 1 SHLR.B #2,Rd 1 SHLR.W Rd 1 SHLR.W #2,Rd 1 SHLR.L ERd 1 SHLR.L #2,ERd 1 SLEEP SLEEP 1 STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 4 STM* SUB Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 STC.W CCR,@ERd 2 1 STC.W EXR,@ERd 2 1 STC.
Appendix A Instruction Set Instruction Fetch I Instruction Mnemonic SUBS SUBS #1/2/4,ERd 1 SUBX SUBX #xx:8,Rd 1 SUBX Rs,Rd 1 TAS 3 TAS @ERd* TRAPA TRAPA #x:2 XOR XORC Notes: 1. 2. 3. 4. Branch Address Read J Stack Operation K 2 Byte Data Access L Word Data Access M Internal Operation N 2 Normal 2 1 1 2/3* 2 Advanced 2 2 1 2/3* 2 XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.
Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle.
Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Internal operation Fetching 4th byte of instruction R:W EA Fetching 1st byte Fetching 2nd byte of branch of branch instruction instruction Figure A.
Appendix A Instruction Set Table A.6 Instruction Execution Cycle Instruction ADD.B #xx:8,Rd 1 2 3 4 5 R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd AND.W Rs,Rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd AND.
Appendix A Instruction Set Instruction 1 2 BMI d:8 R:W NEXT R:W EA BGE d:8 R:W NEXT R:W EA BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA BLE d:8 R:W NEXT R:W EA 3 BRA d:16 (BT d:16) R:W 2nd Internal R:W EA operation, 1 state BRN d:16 (BF d:16) R:W 2nd Internal R:W EA operation, 1 state BHI d:16 R:W 2nd Internal R:W EA operation, 1 state BLS d:16 R:W 2nd Internal R:W EA operation, 1 state BCC d:16 (BHS d:16) R:W 2nd Internal R:W EA operation, 1 state BCS d:16 (BLO d:16) R:W 2nd
Appendix A Instruction Set Instruction 1 2 3 BLT d:16 R:W 2nd Internal R:W EA operation, 1 state BGT d:16 R:W 2nd Internal R:W EA operation, 1 state BLE d:16 R:W 2nd Internal R:W EA operation, 1 state BCLR #xx:3,Rd R:W NEXT 4 BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR#xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BCLR#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
Appendix A Instruction Set Instruction 1 BILD #xx:3,@aa:32 R:W 2nd 2 3 4 R:W 3rd R:W 4th BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIOR #xx:3,Rd R:B EA 6 7 8 9 R:W NEXT BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:16 R:W 2nd R:W 3rd
Appendix A Instruction Set Instruction 1 2 3 4 BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT BNOT #xx:3, @aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BNOT #xx:3, @aa:32 R:W 2nd R:W 3rd R:W 4th 6 W:B EA R:B:M EA R:W:M NEXT BNOT Rn,Rd R:W NEXT BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th BOR #xx:3,Rd R:W NEXT BOR #xx:3,@ERd R:W 2nd R
Appendix A Instruction Set Instruction 1 2 BSR d:8 Advanced R:W NEXT R:W EA BSR d:16 Advanced R:W 2nd 3 W:W:M Stack (H) 4 Internal R:W EA operation, 1 state W:W:M Stack (H) BST #xx:3,Rd R:W NEXT BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST
Appendix A Instruction Set Instruction 1 CMP.B #xx:8,Rd R:W NEXT CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd CMP.W Rs,Rd R:W NEXT CMP.L #xx:32,ERd R:W 2nd CMP.L ERs,ERd R:W NEXT DAA Rd R:W NEXT DAS Rd R:W NEXT DEC.B Rd R:W NEXT DEC.W #1/2,Rd R:W NEXT 2 3 4 5 6 R:W NEXT R:W 3rd R:W NEXT DEC.L #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states DIVXU.
Appendix A Instruction Set Instruction 1 LDC #xx:8,CCR R:W NEXT LDC #xx:8,EXR R:W 2nd LDC Rs,CCR R:W NEXT LDC Rs,EXR R:W NEXT 2 3 4 5 6 7 8 9 R:W NEXT LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA LDC@(d:16,ERs), CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC@(d:16,ERs), EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC@(d:32,ERs), CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LDC@(d:32,ERs), EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LD
Appendix A Instruction Set Instruction MOV.B @(d:32,ERs),Rd 1 R:W 2nd 2 R:W 3rd 3 R:W 4th 4 5 R:W NEXT R:B EA MOV.B @ERs+,Rd R:W NEXT Internal R:B EA operation, 1 state MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA MOV.B Rs,@ERd R:W NEXT W:B EA MOV.B Rs, @(d:16,ERd) R:W 2nd R:W NEXT W:B EA MOV.B Rs, @(d:32,ERd) R:W 2nd R:W 3rd MOV.B Rs,@-ERd R:W NEXT Internal W:B EA operation, 1 state MOV.
Appendix A Instruction Set Instruction 1 MOV.L #xx:32,ERd R:W 2nd 2 3 4 5 R:W 3rd R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th MOV.L @ERs+, ERd R:W 2nd R:W:M NEXT MOV.L @aa:16, ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @aa:32, ERd R:W 2nd R:W:M 3rd R:W 4th MOV.
Appendix A Instruction Set Instruction 1 NOT.L ERd R:W NEXT OR.B #xx:8,Rd R:W NEXT OR.B Rs,Rd R:W NEXT OR.W #xx:16,Rd R:W 2nd OR.W Rs,Rd R:W NEXT 2 3 R:W 2nd R:W 3rd OR.L ERs,ERd R:W 2nd R:W NEXT R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd POP.W Rn R:W NEXT Internal R:W EA operation, 1 state POP.L ERn R:W 2nd PUSH.W Rn R:W NEXT Internal W:W EA operation, 1 state PUSH.L ERn R:W 2nd R:W NEXT ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.W #2,Rd R:W NEXT ROTL.
Appendix A Instruction Set Instruction 1 ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT ROTXR.L ERd R:W NEXT 2 ROTXR.L #2,ERd R:W NEXT RTE R:W NEXT R:W Stack (EXR) RTS Advanced R:W NEXT R:W:M Stack (H) SHAL.B Rd R:W NEXT SHAL.B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.W #2,Rd R:W NEXT SHAL.L ERd R:W NEXT SHAL.L #2,ERd R:W NEXT SHAR.B Rd R:W NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.
Appendix A Instruction Set Instruction SLEEP 1 2 3 4 5 6 R:W NEXT Internal operation :M STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR, @(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR, @(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@-ERd R:W 2nd R:W
Appendix A Instruction Set Instruction 1 SUBS #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd R:W NEXT TAS @ERd*8 R:W 2nd 2 3 R:W NEXT XOR.B Rs,Rd R:W NEXT XOR.W #xx:16,Rd R:W 2nd XOR.W Rs,Rd R:W NEXT 5 6 7 8 9 W:W Stack (EXR) R:W:M VEC R:W VEC+2 Internal R:W* operation, 1 state W:W Stack (EXR) R:W:M VEC R:W VEC+2 Internal R:W*7 operation, 1 state R:W NEXT R:B:M EA W:B EA TRAPA Advanced R:W NEXT Internal W:W #x:2 operation, Stack (L) 1 state XOR.
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FEE8 ICRA ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 H'FEE9 ICR0 Module Name Bus Width Interrupt controller 8 DTC 8 Interrupt controller 8 FLASH 8 ICRB ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 H'FEEA ICRC ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 H'FEEB ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F H'FEEC ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width H'FF8E SCMR1 — — — — SDIR SINV — SMIF SCI1 8 ICDR1 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 IIC1 8 SARX1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX ICMR1 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 FRT 16 8 H'FF8F SAR1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS H'FF90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width H'FFA2 SCR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI2 8 H'FFA3 TDR2 TDRE RDRF ORER FER PER TEND MPB MPBT SCMR2 — — — — SDIR SINV — SMIF DADRBH DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 PWMX 8 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS — REGS OVF WT/IT TME RSTS RST/NMI CKS2 CKS1 CKS0 WDT0 16 Ports 8 H'FFA4 SSR2 H'FFA5 RDR2 H'FF
Appendix B Internal I/O Registers Register Address Name H'FFBE P7PIN (read) H'FFBF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN Ports 8 PBDDR (write) PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR P8DR — P86DR P85DR P84DR P83DR P82DR P81DR P80DR H'FFC0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR H'FFC1 P9DR P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR H
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width H'FFDA SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI0 8 TDRE RDRF ORER FER PER TEND MPB MPBT SMIF H'FFDB TDR0 H'FFDC SSR0 H'FFDD RDR0 H'FFDE SCMR0 — — — — SDIR SINV — ICDR0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 SARX0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 H'FFDF ICMR0 SA
Appendix B Internal I/O Registers Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Bus Width H'FFF4 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF 8 IDR1 TCNTX TMRX TCNTY H'FFF5 ODR1 TMRY ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 TISR — — — — — — — IS TMRY STR1 DBU DBU DBU DBU C/D DBU IBF OBF HIF TCORC H'FFF6 TMRX TCORAX H'FFF7 TCORBX H'FFF8 DADR0 H'FFF9 DADR1 H'FFFA DACR H'FFFC IDR2 TCONRI H'FFFD ODR2 H'FFFE H'FF
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers Lower Address Register Name H8S/2148 Group Register Selection Conditions H8S/2147N Register Selection Conditions H8S/2144 Group Register Selection Conditions Module Name H'FEF3 DTVECR No conditions — — DTC H'FEF4 ABRKCR No conditions No conditions No conditions H'FEF5 BARA Interrupt controller H'FEF6 BARB FLSHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 1 in STCR Flash memory H'FEF7 BARC H'FF80 FLMCR1 H'FF81 FLMCR2 H'FF82 PCSR FLSHE = 0 in STCR
Appendix B Internal I/O Registers Lower Address H'FF94 H'FF95 Register Name H8S/2148 Group Register Selection Conditions H8S/2147N Register Selection Conditions H8S/2144 Group Register Selection Conditions OCRS = 0 in MSTP13 = 0 TOCR OCRS = 0 in MSTP13 = 0 TOCR OCRS = 0 in FRT TOCR OCRBH OCRS = 1 in TOCR OCRS = 1 in TOCR OCRS = 1 in TOCR OCRAL OCRS = 0 in TOCR OCRS = 0 in TOCR OCRS = 0 in TOCR OCRBL OCRS = 1 in TOCR OCRS = 1 in TOCR OCRS = 1 in TOCR OCRAH MSTP13 = 0 H'FF96 TCR H'FF9
Appendix B Internal I/O Registers Lower Address H'FFA1 Register Name H8S/2148 Group Register Selection Conditions H8S/2147N Register Selection Conditions H8S/2144 Group Register Selection Conditions Module Name BRR2 MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR SCI2 DADRAL MSTP11 = 0, IICE = 1 in STCR MSTP11 = 0, IICE = 1 in STCR MSTP11 = 0, IICE = 1 in STCR PWMX H'FFA2 SCR2 MSTP5 = 0 H'FFA3 TDR2 H'FFA4 SSR2 H'FFA5 RDR2 H'FFA6 SCMR2 MSTP5 = 0,
Appendix B Internal I/O Registers Lower Address Register Name H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR H'FFBD P8DDR (write) H8S/2148 Group Register Selection Conditions H8S/2147N Register Selection Conditions H8S/2144 Group Register Selection Conditions Module Name No conditions No conditions No conditions Ports PBPIN (read) H'FFBE P7PIN (read) PBDDR (write) H'FFBF P8DR H'FFC0 P9DDR H'FFC1 P9DR H'FFC2 IER No conditions No conditions No conditions Inte
Appendix B Internal I/O Registers Lower Address Register Name H8S/2148 Group Register Selection Conditions H8S/2144 Group Register Selection Conditions Module Name H'FFD6 PWSL H'FFD7 PWDR0 to PWDR15 H'FFD8 SMR0 ICCR0 H'FFD9 BRR0 MSTP7 = 0, IICE = 0 in STCR ICSR0 MSTP4 = 0, IICE = 1 in STCR MSTP4 = 0, IICE = 1 in STCR — IIC0 H'FFDA SCR0 MSTP7 = 0 MSTP7 = 0 MSTP7 = 0 SCI0 H'FFDB TDR0 H'FFDC SSR0 H'FFDD RDR0 H'FFDE SCMR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR
Appendix B Internal I/O Registers Lower Address H'FFF1 Register Name H8S/2148 Group Register Selection Conditions KMIMR MSTP2 = 0, HIE = 1 in SYSCR TCSRX MSTP8 = 0, HIE = 0 in SYSCR TCSRY H'FFF2 — — TMRX TMRX/Y = 1 in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR Ports — TMRX TMRX/Y = 1 in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in
Appendix B Internal I/O Registers B.3 Functions Register acronym Register name Address to which the register is mapped DACR—D/A Control Register H'FFFA Name of on-chip supporting module D/A Converter Bit numbers Bit Initial bit values 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — Names of the bits. Dashes (—) indicate reserved bits.
Appendix B Internal I/O Registers MRA—DTC Mode Register A Bit Initial value Read/Write H'EC00–H'EFFF DTC 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — DTC data transfer size 0 Byte-size transfer 1 Word-size transfer DTC transfer mode select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC mode 0 0 Normal mode 1 Repeat mode 1 0 Block tra
Appendix B Internal I/O Registers MRB—DTC Mode Register B DTC 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Bit Initial value H'EC00–H'EFFF Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC interrupt select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC chain transfer enable 0 End of DTC data transfer 1 DTC chain tra
Appendix B Internal I/O Registers CRA—DTC Transfer Count Register A Bit 15 Initial value 14 13 12 11 10 H'EC00–H'EFFF 9 8 7 6 5 4 DTC 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined Read/Write — — — — — — — — — — — — CRAH — — — — CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit 15 I
Appendix B Internal I/O Registers IDR3—Input Data Register 3 IDR4—Input Data Register 4 H'FE84 H'FE8C HIF HIF 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value — — — — — — — — Slave R/W R R R R R R R R Host R/W W W W W W W W W Bit Stores host data bus contents at rise of IOW when CS is low ODR3—Output Data Register 3 ODR4—Output Data Register 4 Bit H'FE85 H'FE8D HIF HIF 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 O
Appendix B Internal I/O Registers STR3—Status Register 3 STR4—Status Register 4 H'FE86 H'FE8E HIF HIF 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF Initial value 0 0 0 0 0 0 0 0 Slave R/W R/W R/W R/W R/W R R/W R R/(W) Host R/W R R R R R R R R Bit User-defined bits Output buffer full 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit 1 [Setting condition] When the slave processor writes to ODR Input buffer full
Appendix B Internal I/O Registers KBCRH0—Keyboard Control Register H0 KBCRH1—Keyboard Control Register H1 KBCRH2—Keyboard Control Register H2 Bit H'FED8 H'FEDC H'FEE0 Keyboard Buffer Controller Keyboard Buffer Controller Keyboard Buffer Controller 7 6 5 4 3 2 1 0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS 0 R/(W)* R Initial value 0 1 1 1 0 0 Read/Write R/W R R R/W R/W R/(W)* 0 Keyboard stop 0 0 stop bit received 1 1 stop bit received Parity error 0 [Clearing condition] Read
Appendix B Internal I/O Registers KBCRL0—Keyboard Control Register L0 KBCRL1—Keyboard Control Register L1 KBCRL2—Keyboard Control Register L2 Bit H'FED9 H'FEDD H'FEE1 Keyboard Buffer Controller Keyboard Buffer Controller Keyboard Buffer Controller 7 6 5 4 3 2 1 0 KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0 Initial value 0 1 1 1 0 0 0 0 Read/Write R/W R/W R/W — R R R R Receive counter RXCR3 RXCR2 RXCR1 RXCR0 Receive data contents 0 0 0 0 — 1 1 0 1 1 0 0 1 1 — 1 Start
Appendix B Internal I/O Registers KBBR0—Keyboard Data Buffer Register 0 KBBR1—Keyboard Data Buffer Register 1 KBBR2—Keyboard Data Buffer Register 2 Bit H'FEDA H'FEDE H'FEE2 Keyboard Buffer Controller Keyboard Buffer Controller Keyboard Buffer Controller 7 6 5 4 3 2 1 0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores receive data Rev. 4.
Appendix B Internal I/O Registers KBCOMP—Keyboard Comparator Control Register H'FEE4 IrDA/Expansion A/D 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Keyboard comparator control Bit 3 Bit 2 Bit 1 Bit 0 A/D converter KBADE KBCH2 KBCH1 KBCH0 channel 6 input A/D converter channel 7 input 0 — — — AN6 AN7 1 0 0 0 CIN0 CIN8 1 CIN1 CIN9 0 CIN2 CIN10 1 CIN3 CIN
Appendix B Internal I/O Registers DDCSWR—DDC Switch Register Bit Initial value Read/Write H'FEE6 IIC0 7 6 5 4 3 2 1 0 SWE SW IE IF CLR3 CLR2 CLR1 CLR0 0 0 0 0 1 1 1 1 R/W R/(W)*1 W*2 W*2 W*2 W*2 R/W R/W IIC clear bits Bit 3 Bit 2 Bit 1 Bit 0 Description CLR3 CLR2 CLR1 CLR0 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 0 IIC1 internal latch cleared 1 IIC0 and IIC1 internal latches cleared — Invalid setting 1 1 — — D
Appendix B Internal I/O Registers ICRA—Interrupt Control Register A ICRB—Interrupt Control Register B ICRC—Interrupt Control Register C Bit H'FEE8 H'FEE9 H'FEEA Interrupt Controller Interrupt Controller Interrupt Controller 7 6 5 4 3 2 1 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Interrupt control level 0 Corresponding interrupt source is control level 0 (non-priority) 1 Corresponding interrupt s
Appendix B Internal I/O Registers ISR—IRQ Status Register H'FEEB Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit IRQ7 to IRQ0 flags 0 [Clearing conditions] • Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF • When interrupt exception handling is executed while low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQ
Appendix B Internal I/O Registers ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L H'FEEC H'FEED Interrupt Controller Interrupt Controller ISCRH Bit 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 1 0 IRQ7 to IRQ4 sense control A and B ISCRL Bit 7 6 5 4 3 2 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value 0
Appendix B Internal I/O Registers DTCER—DTC Enable Register H'FEEE to H'FEF2 DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit DTC activation enable 0 DTC activation by interrupt is disabled [Clearing conditions] • When data transfer ends with the DISEL bit set to 1 • When the specified number of transfers end 1 DTC activation by interrupt is enabled [Holding condition] Wh
Appendix B Internal I/O Registers ABRKCR—Address Break Control Register H'FEF4 Interrupt Controller 7 6 5 4 3 2 1 0 CMF — — — — — — BIE Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — — R/W Bit Break interrupt enable 0 Address break disabled 1 Address break enabled Condition match flag 0 [Clearing condition] When address break interrupt exception handling is executed 1 [Setting condition] When address set by BARA to BARC is prefetched while BIE = 1 Rev. 4.
Appendix B Internal I/O Registers BARA—Break Address Register A BARB—Break Address Register B BARC—Break Address Register C Bit BARA H'FEF5 H'FEF6 H'FEF7 Interrupt Controller Interrupt Controller Interrupt Controller 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 A16 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Specifies address (bits 23 to 16) at which address break is to be generated 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'FF80 Flash Memory 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W Bit Program 0 Program mode cleared 1 Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 Erase 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 Program-verify 0 Program-verify mode cleared 1 Transit
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'FF81 Flash Memory 7 6 5 4 3 2 1 0 FLER — — — — — ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — R/W R/W Bit Program setup 0 Program setup cleared 1 Program setup [Setting condition] When SWE = 1 Erase setup 0 Erase setup cleared 1 Erase setup [Setting condition] When SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (erro
Appendix B Internal I/O Registers PCSR—Peripheral Clock Select Register H'FF82 PWM 7 6 5 4 3 — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — R/W R/W — Bit 2 1 PWCKB PWCKA 0 — PWM clock select PWSL Bit 7 PCSR Bit 6 Bit 2 Bit 1 Description PWCKE PWCKS PWCKB PWCKA 0 — — — Clock input is disabled 1 0 — — φ (system clock) is selected 1 0 0 φ/2 is selected 1 φ/4 is selected 0 φ/8 is selected 1 φ/16 is selected 1 Rev. 4.
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 Bit H'FF83 HIF 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W Host interface enable 0 Host interface functions are disabled 1 Host interface functions are enabled CS3 enable 0 Host interface pin channel 3 functions disabled 1 Host interface pin channel 3 functions enabled CS4 enable 0 Host interface pin channel 4 fun
Appendix B Internal I/O Registers EBR1—Erase Block Register 1 EBR2—Erase Block Register 2 H'FF82 H'FF83 Flash Memory Flash Memory Bit 7 6 5 4 3 2 EBR1 — — — — — — Initial value 0 0 0 0 0 0 Read/Write — — — — — — Bit 7 6 5 4 3 2 1 0 1 0 2 * EB9/— EB8/—*2 0 0 1 2 R/W* * R/W*1*2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W*1 R/W R/W R/W R/W R/W R/W R/W EBR2 Notes: 1.
Appendix B Internal I/O Registers SBYCR—Standby Control Register H'FF84 System 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W — R/W R/W R/W Bit System clock select 2 to 0 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock = φ/2 0 Medium-speed clock = φ/4 1 Medium-speed clock = φ/8 0 0 Medium-speed clock = φ/16 1 Medium-speed clock = φ/32 1 — — 1 1 Standby timer select 2 to 0 0 0 0 St
Appendix B Internal I/O Registers LPWRCR—Low-Power Control Register H'FF85 System 7 6 5 4 3 2 1 0 DTON LSON NESEL EXCLE — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W — — — — Bit Subclock input enable 0 Subclock input from EXCL pin is disabled 1 Subclock input from EXCL pin is enabled Noise elimination sampling frequency select 0 Sampling at φ divided by 32 1 Sampling at φ divided by 4 Low-speed on flag 0 • When a SLEEP instruction is execute
Appendix B Internal I/O Registers MSTPCRH—Module Stop Control Register H MSTPCRL—Module Stop Control Register L H'FF86 H'FF87 System System MSTPCRH 7 Bit 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module stop 0 Module stop mode is cleared 1 Module sto
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 SMR0—Serial Mode Register 0 Bit H'FF88 H'FFA0 H'FFD8 SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 1 and 0 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1
Appendix B Internal I/O Registers 2 ICCR1—I C Bus Control Register 1 2 ICCR0—I C Bus Control Register 0 Bit Initial value Read/Write H'FF88 H'FFD8 IIC1 IIC0 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP 0 0 0 0 0 0 0 1 R/W R/(W)* W R/W R/W R/W R/W R/W Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1; writing is ignored I2C bus interface interrupt request
Appendix B Internal I/O Registers BRR1—Bit Rate Register 1 BRR2—Bit Rate Register 2 BRR0—Bit Rate Register 0 H'FF89 H'FFA1 H'FFD9 SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transmit/receive bit rate Rev. 4.
Appendix B Internal I/O Registers 2 ICSR1—I C Bus Status Register 1 2 ICSR0—I C Bus Status Register 0 Bit Initial value Read/Write H'FF89 H'FFD9 IIC1 IIC0 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB 0 0 0 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 0 R/W Acknowledge bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowled
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 SCR2—Serial Control Register 2 SCR0—Serial Control Register 0 Bit H'FF8A H'FFA2 H'FFDA SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 1 and 0 0 0 1 1 0 1 Asynchronous mode Internal clock/SCK pin functions as I/O port Synchronous mode Internal clock/SCK pin functions as serial clock output Async
Appendix B Internal I/O Registers RDR1—Receive Data Register 1 RDR2—Receive Data Register 2 RDR0—Receive Data Register 0 H'FF8D H'FFA5 H'FFDD SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores serial receive data TDR1—Transmit Data Register 1 TDR2—Transmit Data Register 2 TDR0—Transmit Data Register 0 H'FF8B H'FFA3 H'FFDB SCI1 SCI2 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 SSR2—Serial Status Register 2 SSR0—Serial Status Register 0 Bit H'FF8C H'FFA4 H'FFDC SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multi-processor bit is transmitted 1 Data with a 1 multi-processor bit is transmitted Multiprocessor bit 0 [Clearing conditi
Appendix B Internal I/O Registers SCMR1—Serial Interface Mode Register 1 SCMR2—Serial Interface Mode Register 2 SCMR0—Serial Interface Mode Register 0 Bit H'FF8E H'FFA6 H'FFDE SCI1 SCI2 SCI0 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value 1 1 1 1 0 0 1 0 Read/Write — — — — R/W R/W — R/W Serial communication interface mode select 0 Normal SCI mode 1 Setting prohibited Data invert 0 TDR contents are transmitted without modification Receive data is stored in RD
Appendix B Internal I/O Registers 2 ICDR1—I C Bus Data Register 1 2 ICDR0—I C Bus Data Register 0 H'FF8E H'FFDE IIC1 IIC0 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value — — — — — — — — Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit ICDRR Bit ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value — — — — — — — — Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 ICDRS Bit ICDRS7 IC
Appendix B Internal I/O Registers SARX1—Second Slave Address Register 1 SAR1—Slave Address Register 1 SARX0—Second Slave Address Register 0 SAR0—Slave Address Register 0 H'FF8E H'FF8F H'FFDE H'FFDF IIC1 IIC1 IIC0 IIC0 SAR 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Slave address Format select SARX Bit 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Ini
Appendix B Internal I/O Registers 2 ICMR1—I C Bus Mode Register 1 2 ICMR0—I C Bus Mode Register 0 Bit H'FF8F H'FFDF IIC1 IIC0 7 6 5 4 3 2 1 0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit counter BC2 BC1 BC0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 Serial clock select IICX CKS2 0 0 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Synchronous serial format 8 1 2 3 4 5 6 7 I2C bus f
Appendix B Internal I/O Registers TIER—Timer Interrupt Enable Register H'FF90 FRT 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W — Bit Timer overflow interrupt enable 0 Timer overflow interrupt request (FOVI) is disabled 1 Timer overflow interrupt request (FOVI) is enabled Output compare interrupt B enable 0 Output compare interrupt request B (OCIB) is disabled 1 Output compare inte
Appendix B Internal I/O Registers TCSR—Timer Control/Status Register Bit H'FF91 FRT 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Counter clear A 0 1 FRC clearing is disabled FRC is cleared at compare match A Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When FRC changes from H'FFFF to H'0000 Output co
Appendix B Internal I/O Registers FRC—Free-Running Counter H'FF92 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA/OCRB—Output Compare Register A/B H'FF94 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Appendix B Internal I/O Registers TCR—Timer Control Register Bit H'FF96 FRT 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ/2 internal clock source 1 φ/8 internal clock source 1 0 φ/32 internal clock source 1 External clock source (rising edge) Buffer enable B 0 ICRD is not used as a buffer register for input capture B 1 ICRD is used as a buffer register for
Appendix B Internal I/O Registers TOCR—Timer Output Compare Control Register 7 Bit FRT 5 4 3 2 1 0 ICRS OCRS OEA OEB OLVLA OLVLB 6 ICRDMS OCRAMS H'FF97 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output level B 0 0 output at comparematch B 1 1 output at comparematch B Output level A 0 0 output at comparematch A 1 1 output at comparematch A Output enable B 0 Output compare B output disabled 1 Output compare B output enabled Output
Appendix B Internal I/O Registers OCRAR—Output Compare Register AR OCRAF—Output Compare Register AF H'FF98 H'FF9A FRT FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used for OCRA operation when OCRAMS = 1 in TOCR (For details, see section 11.2.4, Output Compare Registers AR and AF (OCRAR, OCRAF).
Appendix B Internal I/O Registers DADRAH—PWM (D/A) Data Register AH DADRAL—PWM (D/A) Data Register AL DADRBH—PWM (D/A) Data Register BH DADRBL—PWM (D/A) Data Register BL H'FFA0 H'FFA1 H'FFA6 H'FFA7 PWMX PWMX PWMX PWMX DADRH DADRL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (data) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — DADRA Initial value DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — 1 Read/Write R
Appendix B Internal I/O Registers DACR—PWM (D/A) Control Register H'FFA0 PWMX 7 6 5 4 3 2 1 0 TEST PWME — — OEB OEA OS CKS Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W Bit Clock select 0 Operates at resolution (T) = system clock cycle time (tcyc) 1 Operates at resolution (T) = system clock cycle time (tcyc) × 2 Output select 0 Direct PWM output 1 Inverted PWM output Output enable A 0 PWM (D/A) channel A output (PWX0 output pin) disabled
Appendix B Internal I/O Registers DACNTH—PWM (D/A) Counter H DACNTL—PWM (D/A) Counter L H'FFA6 H'FFA7 PWMX PWMX DACNTH DACNTL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (counter) 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — — REGS Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — 1 R/W Register select Up-counter Rev. 4.
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 Bit 7 6 5 H'FFA8 4 3 WDT0 2 1 0 OVF WT/IT TME CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W RSTS RST/NMI Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 0 φ/2 1 φ/64 0 φ/128 1 φ/512 0 φ/2048 1 φ/8192 0 φ/32768 1 φ/131072 1 1 0 1 Clock Reset or NMI 0 NMI interrupt requested 1 Internal reset requested Reserved bit Timer enable 0 TCNT is ini
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 H'FFA8 (W), H'FFA9 (R) H'FFEA (W), H'FFEB (R) WDT0 WDT1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Up-counter PAODR—Port A Output Data Register Bit 7 6 H'FFAA 5 4 Port A 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output data for
Appendix B Internal I/O Registers P1PCR—Port 1 MOS Pull-Up Control Register Bit 7 6 5 4 H'FFAC 3 Port 1 2 1 0 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Control of port 1 built-in MOS input pull-ups P2PCR—Port 2 MOS Pull-Up Control Register Bit 7 6 5 4 H'FFAD 3 Port 2 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R
Appendix B Internal I/O Registers P2DDR—Port 2 Data Direction Register Bit 7 6 5 H'FFB1 4 Port 2 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of input or output for port 2 pins P1DR—Port 1 Data Register H'FFB2 Port 1 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W B
Appendix B Internal I/O Registers P4DDR—Port 4 Data Direction Register Bit 7 6 5 H'FFB5 4 Port 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of input or output for port 4 pins P3DR—Port 3 Data Register Bit H'FFB6 Port 3 7 6 5 4 3 2 1 0 P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/
Appendix B Internal I/O Registers P6DDR—Port 6 Data Direction Register Bit 7 6 5 H'FFB9 4 Port 6 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Specification of input or output for port 6 pins P5DR—Port 5 Data Register Bit H'FFBA Port 5 7 6 5 4 3 2 1 0 — — — — — P52DR P51DR P50DR Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — R/W R/W R/W Output data for port 5 pins
Appendix B Internal I/O Registers P8DDR—Port 8 Data Direction Register Bit 7 — 6 5 H'FFBD (W) 4 3 Port 8 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W Specification of input or output for port 8 pins PBPIN—Port B Input Data Register Bit 7 6 H'FFBD (R) 5 4 3 Port B 2 1 0 PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R
Appendix B Internal I/O Registers P8DR—Port 8 Data Register H'FFBF Port 8 7 6 5 4 3 2 1 0 — P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial value 1 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W Bit Output data for port 8 pins P9DDR—Port 9 Data Direction Register Bit 7 6 5 H'FFC0 4 Port 9 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Mode 1 Initial value 0 1 0 0 0 0 0 0 Read/Write W W W W W W W W Initial value 0
Appendix B Internal I/O Registers IER—IRQ Enable Register H'FFC2 Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit IRQ7 to IRQ0 enable 0 IRQn interrupt disabled 1 IRQn interrupt enabled (n = 7 to 0) Rev. 4.
Appendix B Internal I/O Registers STCR—Serial Timer Control Register H'FFC3 System 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Internal Clock Source Select*1 Reserved bit Flash memory control register enable 0 Flash memory control register not selected 1 Flash memory control register selected I2C master enable 0 CPU access to SCI0, SCI1, and SCI2 control registers is enabled
Appendix B Internal I/O Registers SYSCR—System Control Register H'FFC4 System 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Bit Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled Host interface enable 0 Addresses H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF are used for access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection
Appendix B Internal I/O Registers MDCR—Mode Control Register H'FFC5 System 7 6 5 4 3 2 1 0 EXPE — — — — — MDS1 MDS0 Initial value —* 0 0 0 0 0 —* —* Read/Write R/W* — — — — — R R Bit Mode select 1 and 0 Expanded mode enable 0 Single-chip mode selected 1 Expanded mode selected Note: * Determined by the MD1 and MD0 pins. Rev. 4.
Appendix B Internal I/O Registers BCR—Bus Control Register H'FFC6 7 6 ICIS1 ICIS0 Initial value 1 1 0 1 Read/Write R/W R/W R/W R/W Bit 5 4 Bus Controller 3 2 1 0 — IOS1 IOS0 0 1 1 1 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 IOS select Address for which AS/IOS pin IOS1 IOS0 output goes low when IOSE = 1 0 1 0 Low in access to address H'(FF)F000 to H'(FF)F03F 1 Low in access to address H'(FF)F000 to H'(FF)F0FF 0 Low in access to address H'(FF)F000 to H'(FF)F3FF 1 Low i
Appendix B Internal I/O Registers WSCR—Wait State Control Register H'FFC7 Bus Controller 7 6 5 4 3 2 1 0 RAMS RAM0 ABW AST WMS1 WMS0 WC1 WC0 Initial value 0 0 1 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Wait count 1 and 0 0 1 Reserved bits 0 No program wait states are inserted 1 1 program wait state is inserted in external memory space accesses 0 2 program wait states are inserted in external memory space accesses 1 3 program wait states are in
Appendix B Internal I/O Registers TCR0—Timer Control Register 0 TCR1—Timer Control Register 1 TCRX—Timer Control Register X TCRY—Timer Control Register Y H'FFC8 H'FFC9 H'FFF0 H'FFF0 TMR0 TMR1 TMRX TMRY 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 Channel Bit 2 Bit 1 Bit 0 Description CKS2 CKS1 CKS0 Counter clear 1 and 0 0 1 0 1 0 0 Clear is disabled
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR0 Bit H'FFCA TMR0 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 out
Appendix B Internal I/O Registers TCSR1—Timer Control/Status Register 1 TCSR1 Bit H'FFCB TMR1 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 output a
Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORAY—Time Constant Register AY TCORBY—Time Constant Register BY TCORC—Time Constant Register C TCORAX—Time Constant Register AX TCORBX—Time Constant Register BX H'FFCC H'FFCD H'FFCE H'FFCF H'FFF2 H'FFF3 H'FFF5 H'FFF6 H'FFF7 TMR0 TMR1 TMR0 TMR1 TMRY TMRY TMRX TMRX TMRX TCORA0 TCORB0 TCORA1 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNTX—Timer Counter X TCNTY—Timer Counter Y H'FFD0 H'FFD1 H'FFF4 H'FFF4 TMR0 TMR1 TMRX TMRY TCNT0 TCNT1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TCNTX, TCNTY Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W
Appendix B Internal I/O Registers PWOERA—PWM Output Enable Register A PWOERB—PWM Output Enable Register B H'FFD3 H'FFD2 PWM PWM 7 6 5 4 3 2 1 0 PWOERA OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Bit Bit PWOERB Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Switching between PWM output and port ou
Appendix B Internal I/O Registers PWSL—PWM Register Select 7 Bit H'FFD6 6 PWCKE PWCKS PWM 5 4 3 2 1 0 — — RS3 RS2 RS1 RS0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W Register Select 0 0 0 0 PWDR0 selected 1 PWDR1 selected 1 0 PWDR2 selected 1 PWDR3 selected 1 0 0 PWDR4 selected 1 PWDR5 selected 1 0 PWDR6 selected 1 PWDR7 selected 1 0 0 0 PWDR8 selected 1 PWDR9 selected 1 0 PWDR10 selected 1 PWDR11 selected 1 0 0 PWDR12 selected
Appendix B Internal I/O Registers PWDR0 to PWDR15—PWM Data Registers H'FFD7 PWM Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Specifies duty factor of basic output pulse and number of additional pulses ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL H'FFE0
Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register H'FFE8 A/D Converter 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel select Group selection Channel selection Description CH2 CH1 CH0 0 0 0 AN0 AN0 1 AN1 AN0, AN1 0 AN2 AN0, AN1, AN2 1 AN3 AN0, AN1, AN2, AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 or CIN0 to 7 AN4, AN5, AN6 or CIN0 to 7 1 AN7
Appendix B Internal I/O Registers ADCR—A/D Control Register H'FFE9 A/D Converter 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — — — — — Initial value 0 0 1 1 1 1 1 1 Read/Write R/W R/W — — — — — — Bit Timer trigger select 0 1 0 Start of A/D conversion by external trigger is disabled 1 Start of A/D conversion by external trigger is disabled 0 Start of A/D conversion by external trigger (8-bit timer) is enabled 1 Start of A/D conversion by external trigger pin is enabled Rev.
Appendix B Internal I/O Registers TCSR1—Timer Control/Status Register 1 Bit H'FFEA WDT1 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)*1 R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock 0 φ/2 1 φ/64 0 φ/128 1 φ/512 0 φ/2048 1 φ/8192 0 φ/32768 1 φ/131072 0 φSUB/2 1 φSUB/4 0 φSUB/8 1 φSUB/16 0 φSUB/32 1 φSUB/64 0 φSUB/128
Appendix B Internal I/O Registers HICR—Host Interface Control Register H'FFF0 HIF 7 6 5 4 3 2 — — — — — IBFIE2 Initial value 1 1 1 1 1 0 0 0 Slave R/W — — — — — R/W R/W R/W Host R/W — — — — — — — — Bit 0 1 IBFIE1 FGA20E Fast gate A20 enable 0 Fast gate A20 function disabled 1 Fast gate A20 function enabled Input data register full interrupt enable 1 0 Input data register (IDR1) receive complete interrupt is disabled 1 Input data register (IDR1) receive c
Appendix B Internal I/O Registers TCSRX—Timer Control/Status Register X TCSRX Bit H'FFF1 TMRX 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 o
Appendix B Internal I/O Registers TCSRY—Timer Control/Status Register Y TCSRY Bit H'FFF1 TMRY 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W Output select 1 and 0 0 1 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 No change at compare match B 1 0 out
Appendix B Internal I/O Registers KMIMR—Keyboard Matrix Interrupt Mask Register KMIMRA—Keyboard Matrix Interrupt Mask Register A H'FFF1 H'FFF3 Interrupt Controller Interrupt Controller KMIMR Bit 7 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Keyboard matrix interrupt mask 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled KMIMRA Bit 7
Appendix B Internal I/O Registers KMPCR—Port 6 MOS Pull-Up Control Register Bit 7 6 5 4 H'FFF2 3 Port 6 2 1 0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Control of port 6 built-in MOS input pull-ups Note: KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. When selecting KMPCR, set the HIE bit to 1 in SYSCR.
Appendix B Internal I/O Registers TISR—Timer Input Select Register H'FFF5 TMRY 7 6 5 4 3 2 1 0 — — — — — — — IS Initial value 1 1 1 1 1 1 1 0 Read/Write — — — — — — — R/W Bit Input select 0 IVG signal is selected (H8S/2148 Group) External clock/reset input is disabled (H8S/2144 Group, H8S/2147N) 1 VSYNCI/TMIY (TMCIY/TMRIY) is selected Rev. 4.
Appendix B Internal I/O Registers STR1—Status Register 1 STR2—Status Register 2 H'FFF6 H'FFFE HIF HIF 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF Initial value 0 0 0 0 0 0 0 0 Slave R/W R/W R/W R/W R/W R R/W R R/(W) Host R/W R R R R R R R R Bit User-defined bits Output buffer full 0 [Clearing condition] When the host processor reads ODR 1 [Setting condition] When the slave processor writes to ODR Input buffer full 0 [Clearing condition] When the slav
Appendix B Internal I/O Registers DACR—D/A Control Register H'FFFA D/A Converter 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — Bit D/A enabled DAOE1 DAOE0 0 1 DAE Conversion result 0 * Channel 0 and 1 D/A conversion disabled 1 0 Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 Channel 0 and 1 D/A conversion enabled 0 Channel 0 D/A conversion disabled Channel 1 D/A conversion ena
Appendix B Internal I/O Registers TCONRI—Timer Connection Register I Bit 7 6 H'FFFC 5 SIMOD1 SIMOD0 SCONE Timer Connection 4 3 2 1 0 ICST HFINV VFINV HIINV VIINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Input synchronization signal inversion 0 The VSYNCI pin state is used directly as the VSYNCI input 1 The VSYNCI pin state is inverted before use as the VSYNCI input Input synchronization signal inversion 0 The HSYNCI and CSYNCI pin stat
Appendix B Internal I/O Registers TCONRO—Timer Connection Register O Bit H'FFFD Timer Connection 7 6 5 4 3 2 1 HOE VOE CLOE CBOE HOINV VOINV 0 CLOINV CBOINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output synchronization signal inversion 0 The CBLANK signal is used directly as the CBLANK output 1 The CBLANK signal is inverted before use as the CBLANK output Output synchronization signal inversion 0 The CLO signal (CL1, CL2, CL3, or CL
Appendix B Internal I/O Registers TCONRS—Timer Connection Register S 7 Bit 6 TMRX/Y 5 H'FFFE 4 3 Timer Connection 2 1 0 ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clamp waveform mode select 1 and 0 ISGENE CLMOD1 CLMOD0 0 0 1 Description 0 The CL1 signal is selected 1 The CL2 signal is selected 0 The CL3 signal is selected 1 1 0 The CL4 signal is selected 0 1 1 0 1 Vertical synchroniza
Appendix B Internal I/O Registers SEDGR—Edge Sense Register Bit 7 6 5 VEDG HEDG CEDG Initial value Read/Write H'FFFF 0 0 R/(W)*1 4 3 2 HFEDG VFEDG PREQF 0 R/(W)*1 Timer Connection 0 0 R/(W)*1 R/(W)*1 R/(W)*1 0 R/(W)*1 1 0 IHI IVI —*2 —*2 R R IVI signal level 0 The IVI signal is low 1 The IVI signal is high IHI signal level 0 The IHI signal is low 1 The IHI signal is high Pre-equalization flag 0 [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 1
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Mode 2, 3 EXPE Mode 1 RP1P Hardware standby Mode 1 WP1P Reset R D Q P1nDDR * C WP1D Reset P1n R Q D P1nDR C WP1 RP1 Legend: WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 Notes: n = 0 to 7 * Set priority Figure C.1 Port 1 Block Diagram Rev. 4.
Appendix C I/O Port Block Diagrams C.2 Port 2 Block Diagrams Mode 2, 3 EXPE Mode 1 RP2P Hardware standby Mode 1 WP2P Reset R D Q P2nDDR * C WP2D Reset P2n Internal address bus R Q D P2nPCR C Internal data bus Reset 8-bit PWM PWM output enable PWM output R Q D P2nDR C WP2 RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Notes: n = 0 to 3 * Set priority Figure C.2 Port 2 Block Diagram (Pins P20 to P23) Rev. 4.
Appendix C I/O Port Block Diagrams Mode 2, 3 EXPE IOSE Mode 1 RP2P Hardware standby Mode 1 WP2P Reset R D Q P2nDDR * C WP2D Reset P2n R Q D P2nDR C WP2 RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Notes: n = 4 to 6 * Set priority Figure C.3 Port 2 Block Diagram (Pins P24 to P26) Rev. 4.
Appendix C I/O Port Block Diagrams Mode 2, 3 EXPE IOSE Mode 1 RP2P Hardware standby Mode 1 WP2P Reset R D Q P27DDR * C WP2D Reset P27 Internal address bus R Q D P27PCR C Internal data bus Reset 8-bit PWM PWM output enable PWM output R Q D P27DR C Mode 2, 3 WP2 Timer connection CBLANK CBLANK output enable RP2 Legend: WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 Note: * Set priority Figure C.4 Port 2 Block Diagram (Pin P27) Rev. 4.
Appendix C I/O Port Block Diagrams C.3 Port 3 Block Diagram Mode 2, 3 EXPE HI12E Mode 1 RP3P Hardware standby CS IOR WP3P Reset R D Q P3nDDR C External address write WP3D Reset P3n CS IOW R Q D P3nDR C WP3 RP3 External address read Legend: WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 Note: n = 0 to 7 Figure C.5 Port 3 Block Diagram Rev. 4.
Appendix C I/O Port Block Diagrams Port 4 Block Diagrams Hardware standby Reset R D Q P40DDR C WP4D Internal data bus C.4 SCI2 TxD2/IrTxD Transmit enable Reset P40 R Q D P40DR C WP4 RP4 8-bit timer 0 Counter clock input Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.6 Port 4 Block Diagram (Pin P40) Rev. 4.
Hardware standby Reset R D Q P41DDR C WP4D Internal data bus Appendix C I/O Port Block Diagrams 8-bit timer 0 8-bit timer output Output enable Reset P41 R Q D P41DR C WP4 RP4 SCI2 Receive enable RxD2/IrRxD Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.7 Port 4 Block Diagram (Pin P41) Rev. 4.
Hardware standby Reset R D Q P42DDR C Internal data bus Appendix C I/O Port Block Diagrams WP4D SCI2 Input enable Clock output Output enable Reset Clock output *1 R Q D P42DR C P42 *2 WP4 IIC1 SDA1 output Transmit enable RP4 SDA1 input 8-bit timer 0 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Reset input Notes: 1. Output enable signal 2. Open drain control signal Figure C.8 Port 4 Block Diagram (Pin P42) Rev. 4.
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P43DDR C WP4D Reset R Host interface RESOBF2 (resets HIRQ11) Q D P43DR C P43 WP4 RP4 8-bit timer 1 Counter clock input Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.9 Port 4 Block Diagram (Pin P43) Rev. 4.
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P44DR C WP4D Timer connection HSYNCO output Output enable Reset R Q D P44DR C P44 WP4 Host interface RESOBF1 (resets HIRQ1) 8-bit timer 1 TMO1 output Output enable RP4 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.10 Port 4 Block Diagram (Pin P44) Rev. 4.
Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Reset R D Q P45DDR C WP4D Reset R Host interface RESOBF1 (resets HIRQ12) Q D P45DR C P45 WP4 RP4 8-bit timer 1 Timer reset input Timer connection Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.11 Port 4 Block Diagram (Pin P45) Rev. 4.
Hardware standby Reset R D Q P4nDDR C WP4D Internal data bus Appendix C I/O Port Block Diagrams 14-bit PWM PWX0, PWX1 output Output enable Reset P4n R Q D P4nDR C WP4 RP4 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Note: n = 6 or 7 Figure C.12 Port 4 Block Diagram (Pins P46, P47) Rev. 4.
Appendix C I/O Port Block Diagrams Port 5 Block Diagrams Hardware standby Reset R D Q P50DDR C WP5D Internal data bus C.5 SCI0 Serial transmit data Output enable Reset P50 R Q D P50DR C WP5 RP5 Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.13 Port 5 Block Diagram (Pin P50) Rev. 4.
Hardware standby Reset R D Q P51DDR C Internal data bus Appendix C I/O Port Block Diagrams WP5D SCI0 Input enable Reset R Q D P51DR C P51 WP5 RP5 Serial receive data Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.14 Port 5 Block Diagram (Pin P51) Rev. 4.
Hardware standby Reset R D Q P52DDR C WP5D *1 Reset R Q D P52DR C P52 *2 WP5 Internal data bus Appendix C I/O Port Block Diagrams SCI0 Input enable Clock output Output enable Clock input IIC0 SCL0 output Transmit enable RP5 SCL0 input Legend: WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Notes: 1. Output enable signal 2. Open drain control signal Figure C.15 Port 5 Block Diagram (Pin P52) Rev. 4.
Appendix C I/O Port Block Diagrams C.
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset Internal data bus Reset R D Q P61DDR C WP6D 16-bit FRT FTOA output Output enable Reset R Q D P61DR C P61 WP6 Timer connection VSYNCO output Output enable RP6 Key-sense interrupt input KMIMR1 A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.17 Port 6 Block Diagram (Pin P61) Rev. 4.
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P64DDR C WP6D Internal data bus Reset Timer connection CLAMPO output Output enable Reset P64 R Q D P64DR C WP6 RP6 16-bit FRT FTIC input Key-sense interrupt input KMIMR4 A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.18 Port 6 Block Diagram (Pin P64) Rev. 4.
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P66DDR C WP6D Internal data bus Reset 16-bit FRT FTOB output Output enable Reset P66 R Q D P66DR C WP6 RP6 KMIMR6 Other key-sense interrupt inputs IRQ6 input IRQ6 enable A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.19 Port 6 Block Diagram (Pin P66) Rev. 4.
Appendix C I/O Port Block Diagrams R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P67DDR C WP6D Internal data bus Reset 8-bit timer X TMOX output Output enable Reset P67 R Q D P67DR C WP6 RP6 KMIMR7 Other key-sense interrupt inputs IRQ7 input IRQ7 enable A/D converter Analog input Legend: WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 Figure C.20 Port 6 Block Diagram (Pin P67) Rev. 4.
Appendix C I/O Port Block Diagrams Port 7 Block Diagrams RP7 P7n Internal data bus C.7 A/D converter Analog input Legend: RP7: Read port 7 Note: n = 0 to 5 RP7 P7n Internal data bus Figure C.21 Port 7 Block Diagram (Pins P70 to P75) A/D converter Analog input D/A converter Output enable Analog output Legend: RP7: Read port 7 Note: n = 6 or 7 Figure C.22 Port 7 Block Diagram (Pins P76, P77) Rev. 4.
Appendix C I/O Port Block Diagrams Port 8 Block Diagrams HI12E EXPE Mode 2, 3 Hardware standby Reset R D Q P80DDR C Internal data bus C.8 WP8D Reset R Q D P80DR C P80 WP8 RP8 HIF HA0 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.23 Port 8 Block Diagram (Pin P80) Rev. 4.
Reset Hardware standby Mode 2, 3 EXPE CS2E HI12E R D Q P81DDR C WP8D Internal data bus Appendix C I/O Port Block Diagrams HIF GA20 output Output enable Reset P81 R Q D P81DR C WP8 RP8 HIF CS2 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.24 Port 8 Block Diagram (Pin P81) Rev. 4.
Hardware standby Reset R D Q P8nDDR C Internal data bus Appendix C I/O Port Block Diagrams WP8D Reset R Q D P8nDR C P8n WP8 RP8 HIF Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 HIFSD input Mode 2, 3 EXPE (P82 only) HI12E Note: n = 2, 3 Figure C.25 Port 8 Block Diagram (Pins P82, P83) Rev. 4.
Hardware standby Reset R D Q P84DDR C WP8D Internal data bus Appendix C I/O Port Block Diagrams SCI1 TxD1 Transmit enable Reset P84 R Q D P84DR C WP8 RP8 IRQ3 input IRQ3 enable Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.26 Port 8 Block Diagram (Pin P84) Rev. 4.
Hardware standby Reset R D Q P85DDR C Internal data bus Appendix C I/O Port Block Diagrams SCI1 WP8D Input enable Reset R Q D P85DR C P85 WP8 RP8 Serial receive data IRQ4 input IRQ4 enable Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.27 Port 8 Block Diagram (Pin P85) Rev. 4.
Hardware standby Reset Internal data bus Appendix C I/O Port Block Diagrams R D Q P86DDR C WP8D *1 Reset SCI1 Input enable Clock output Output enable Clock input R Q D P86DR C P86 *2 WP8 IIC1 SCL1 output Transmit enable RP8 SCL1 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Notes: 1. Output enable signal 2. Open drain control signal Figure C.28 Port 8 Block Diagram (Pin P86) Rev. 4.
Appendix C I/O Port Block Diagrams Port 9 Block Diagrams Hardware standby EXPE Mode 2, 3 GA20 HI12E CS2E EXPE ABW Reset R D Q P90DDR C Internal data bus C.9 WP9D Bus controller LWR output Reset P90 R Q D P90DR C WP9 RP9 HIF ECS2 input A/D converter External trigger input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 IRQ2 input IRQ2 enable Figure C.29 Port 9 Block Diagram (Pin P90) Rev. 4.
Hardware standby Reset R D Q P9nDDR C Internal data bus Appendix C I/O Port Block Diagrams WP9D Reset R Q D P9nDR C P9n WP9 RP9 Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 1 or 2 Figure C.30 Port 9 Block Diagram (Pins P91, P92) Rev. 4.
Hardware standby Mode 2, 3 EXPE HI12E EXPE Reset Internal data bus Appendix C I/O Port Block Diagrams R D Q P9nDDR C WP9D Reset P9n Bus controller RD output HWR output AS/IOS output R Q D P9nDR C WP9 RP9 HIF Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Mode 2, 3 EXPE HI12E IOR input IOW input CS1 input Note: n = 3 to 5 Figure C.31 Port 9 Block Diagram (Pins P93 to P95) Rev. 4.
Reset Mode 1 Internal data bus Appendix C I/O Port Block Diagrams Hardware standby S R D Q P96DDR C Subclock input enable WP9D ø output P96 RP9 Subclock input Legend: WP9D: Write to P9DDR RP9: Read port 9 Figure C.32 Port 9 Block Diagram (Pin P96) Rev. 4.
Hardware standby Reset R D Q P97DDR C WP9D Internal data bus Appendix C I/O Port Block Diagrams Bus controller Input enable EXPE *1 Reset R Q D P97DR C P97 *2 WP9 WAIT input IIC0 SDA0 output Transmit enable RP9 SDA0 input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Notes: 1. Output enable signal 2. Open drain control signal Figure C.33 Port 9 Block Diagram (Pin P97) Rev. 4.
Appendix C I/O Port Block Diagrams Hardware standby Reset Mode 2 EXPE IOSE R D Q PAnDDR C Internal address bus Port A Block Diagrams Internal data bus C.10 WPAD PAn Reset R Q D PAnODR C WPA RPAO RPA Key-sense interrupt input KMIMR n+8 A/D converter Analog input Legend: WPAD: WPA: RPAO: RPA: Write to PADDR Write to PAODR Read PAODR Read port A Note: n = 0 or 1 Figure C.34 Port A Block Diagram (Pins PA0, PA1) Rev. 4.
Reset Mode 2 EXPE IOSE R D Q PAnDDR C WPAD *1 Internal address bus Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Keyboard buffer controller Output enable Output PAn *2 Reset R Q D PAnODR C RPAO WPA RPA Input Key-sense interrupt input KMIMR n+8 A/D converter Analog input Legend: WPAD: WPA: RPAO: RPA: Write to PADDR Write to PAODR Read PAODR Read port A Notes: n = 2 or 3 1. Output enable signal 2. Open-drain control signal Figure C.
IICS Mode 2 EXPE IOSE Reset R D Q PAnDDR C WPAD *1 Internal address bus Hardware standby Internal data bus Appendix C I/O Port Block Diagrams Keyboard buffer controller Output enable Output PAn *2 Reset R Q D PAnODR C RPAO WPA RPA Input Key-sense interrupt input KMIMR n+8 A/D converter Analog input Legend: WPAD: WPA: RPAO: RPA: Write to PADDR Write to PAODR Read PAODR Read port A Notes: n = 4 to 7 1. Output enable signal 2. Open-drain control signal Figure C.
Appendix C I/O Port Block Diagrams Port B Block Diagram Reset Hardware standby External address write EXPE ABW Internal data bus C.11 R D Q PBnDDR C WPBD (D0, D1) Reset Host interface PBn R Q D PBnODR C RPBO RESOBF3, 4 (Reset HIRQ3, HIRQ4) WPB External address read (D0, D1) RPB Legend: WPBD: WPB: RPBO: RPB: Write to PBDDR Write to PBODR Read PBODR Read port B Note: n = 0, 1 Figure C.37 Port B Block Diagram (Pins PB0 and PB1) Rev. 4.
Mode 2, 3 EXPE CS input enable HI12E Hardware standby Reset External address write EXPE ABW Internal data bus Appendix C I/O Port Block Diagrams R D Q PBnDDR C WPBD (D2, D3) Reset PBn R Q D PBnODR C RPBO WPB External address read (D2, D3) RPB HIF Legend: WPBD: Write to PBDDR WPB: Write to PBODR RPBO: Read PBODR RPB: Read port B Note: n = 2, 3 Figure C.38 Port B Block Diagram (Pins PB2 and PB3) Rev. 4.
Reset Hardware standby External address write EXPE ABW R D Q PBnDDR C Internal data bus Appendix C I/O Port Block Diagrams WPBD (D7 to D4) Reset PBn R Q D PBnODR C RPBO WPB External address read (D7 to D4) RPB Legend: WPBD: Write to PBDDR WPB: Write to PBODR RPBO: Read PBODR RPB: Read port B Note: n = 4 to 7 Figure C.39 Port B Block Diagram (Pins PB4 to PB7) Rev. 4.
Appendix D Pin States Appendix D Pin States D.1 Port States in Each Processing State Table D.
Appendix D Pin States Port Name Pin Name Port 96 φ EXCL Hardware Software MCU Operating Standby Standby Mode Reset Mode Mode 1 Clock T output [DDR = 1] H 2, 3 (EXPE = 1) T [DDR = 0] T 2, 3 (EXPE = 0) Port 95 to 93 AS, HWR, RD 1 H 2, 3 (EXPE = 1) T T 2, 3 (EXPE = 0) Port 92 to 91 1 Watch Mode Sleep Mode EXCL input [DDR = 1] clock output Subsleep Mode Subactive Mode Program Execution State EXCL input EXCL input Clock output/ EXCL input/ input port [DDR = 0] T H H H H AS, HWR, RD
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode E.1 Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must remain low until STBY signal goes low (minimum delay from STBY low to RES high: 0 ns).
Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.
Appendix F Product Code Lineup Product Type H8S/2147N H8S/2147N F-ZTAT version Standard product (5-V version) Low-voltage version (3-V version) H8S/2144 Group H8S/2144 Mask-ROM version F-ZTAT version H8S/2143 H8S/2142 Mask-ROM version Mask-ROM version F-ZTAT version H8S/2144A F-ZTAT version A-mask version HD64F2147NFA20 100-pin QFP (FP-100B) HD64F2147NTE20 100-pin TQFP (TFP-100B) HD64F2147NVFA10 100-pin QFP (FP-100B) HD64F2147NVTE10 100-pin TQFP (TFP-100B) HD6432144S(V)(***)FA 100-p
Appendix G Package Dimensions Appendix G Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 NOTE 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix G Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 75 51 76 NOTE 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 50 bp c c1 HE *2 E b1 Reference Dimension in Millimeters Symbol Terminal cross section ZE Min 1 A 25 ZD c 100 A2 26 Index mark θ F A1 L L1 Detail F e y *3 bp x M Figure G.2 Package Dimensions (TFP-100B) Rev. 4.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2148 Group, H8S/2144 Group, H8S/2148FZTAT™, H8S/2147N F-ZTAT™, H8S/2144F-ZTAT™, H8S/2142F-ZTAT™ Publication Date: 1st Edition, November 1999 Rev.4.00, September 27, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2148 Group, H8S/2144 Group, H8S/2148F-ZTAT™, H8S/2147N F-ZTAT™, H8S/2144F-ZTAT™, H8S/2142F-ZTAT™ Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0327-0400