Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 16-Bit 20 MHz I/O number 74

1051

Appendix B Internal I/O Registers

Rev. 4.00 Sep 27, 2006 page 1006 of 1130

REJ09B0327-0400

MRB—DTC Mode Register B H'EC00–H'EFFF DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC interrupt select

0 After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

1 After a data transfer ends, the CPU interrupt is

enabled

DTC chain transfer enable

0 End of DTC data transfer

1 DTC chain transfer

SAR—DTC Source Address Register H'EC00–H'EFFF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specifies DTC transfer data source address

DAR—DTC Destination Address Register H'EC00–H'EFFF DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specifies DTC transfer data destination address