Datasheet
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1035 of 1130
REJ09B0327-0400
SSR1—Serial Status Register 1 H'FF8C SCI1
SSR2—Serial Status Register 2 H'FFA4 SCI2
SSR0—Serial Status Register 0 H'FFDC SCI0
7
TDRE
1
R/(W)
*
6
RDRF
0
R/(W)
*
5
ORER
0
R/(W)
*
4
FER
0
R/(W)
*
3
PER
0
R/(W)
*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
Read/Write
Multiprocessor bit transfer
0
Data with a 0 multi-processor
bit is transmitted
1 Data with a 1 multi-processor
bit is transmitted
Note: * Only 0 can be written, to clear the flag.
Multiprocessor bit
0
[Clearing condition]
When data with a 0 multiprocessor
bit is received
1 [Setting condition]
When data with a 1 multiprocessor
bit is received
Transmit end
0
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Parity error
0
[Clearing condition]
When 0 is written in PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Framing error
0
[Clearing condition]
When 0 is written in FER after reading FER = 1
1 [Setting condition]
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
Overrun error
0
[Clearing condition]
When 0 is written in ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1
Receive data register full
0
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Transmit data register empty
0
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR