Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1085 of 1130
REJ09B0327-0400
SEDGR—Edge Sense Register H'FFFF Timer Connection
Bit
Initial value
Read/Write
7
VEDG
0
R/(W)
6
HEDG
0
R/(W)
5
CEDG
0
R/(W)
4
HFEDG
0
R/(W)
3
VFEDG
0
R/(W)
0
IVI
—
*2
R
2
PREQF
0
R/(W)
1
IHI
—
*
2
R
*
1
*
1
*
1
*
1
*
1
*
1
IVI signal level
0
The IVI signal is low
1 The IVI signal is high
Notes: 1.
2.
IHI signal level
0
The IHI signal is low
1 The IHI signal is high
Pre-equalization flag
0
[Clearing condition]
When 0 is written in PREQF after
reading PREQF = 1
1 [Setting condition]
When an IHI signal 2fH modification
condition is detected
VFBACKI edge
0
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
1 [Setting condition]
When a rising edge is detected on the VFBACKI pin
HFBACKI edge
0
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1 [Setting condition]
When a rising edge is detected on the HFBACKI pin
CSYNCI edge
0
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
1 [Setting condition]
When a rising edge is detected on the CSYNCI pin
HSYNCI edge
0
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1 [Setting condition]
When a rising edge is detected on the HSYNCI pin
VSYNCI edge
0
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1 [Setting condition]
When a rising edge is detected on the VSYNCI pin
Only 0 can be written, to clear the flags.
The initial value is undefined since it depends on the pin states.