Datasheet

Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 79 of 1130
REJ09B0327-0400
Bus cycle
T1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High impedance
Figure 2.18 Pin States during On-Chip Memory Access