Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 116 of 1130
REJ09B0327-0400
5.1.4 Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address
*
1
System control register SYSCR R/W H'09 H'FFC4
IRQ sense control register H ISCRH R/W H'00 H'FEEC
IRQ sense control register L ISCRL R/W H'00 H'FEED
IRQ enable register IER R/W H'00 H'FFC2
IRQ status register ISR R/(W)
*
2
H'00 H'FEEB
Keyboard matrix interrupt mask
register
KMIMR R/W H'BF H'FFF1
*
3
Keyboard matrix interrupt mask
register A
KMIMRA R/W H'FF H'FFF3
*
3
Interrupt control register A ICRA R/W H'00 H'FEE8
Interrupt control register B ICRB R/W H'00 H'FEE9
Interrupt control register C ICRC R/W H'00 H'FEEA
Address break control register ABRKCR R/W H'00 H'FEF4
Break address register A BARA R/W H'00 H'FEF5
Break address register B BARB R/W H'00 H'FEF6
Break address register C BARC R/W H'00 H'FEF7
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
3. When setting KMIMR and KMIMRA, the HIE bit in SYSCR must be set to 1, and also
MSTP2 bit in MSTPCRL must be set to 0.