Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 166 of 1130
REJ09B0327-0400
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
Undefined
D7 to D0
Valid
Write
HIgh
Figure 6.8 16-Bit, 2-State Access Space Bus Timing (2)
(Odd Address Byte Access)
