Datasheet

Rev. 4.00 Sep 27, 2006 page xxvi of xliv
2.8.5 Bus-Released State............................................................................................... 76
2.8.6 Power-Down State ............................................................................................... 77
2.9 Basic Timing..................................................................................................................... 78
2.9.1 Overview.............................................................................................................. 78
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 78
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 80
2.9.4 External Address Space Access Timing .............................................................. 81
2.10 Usage Note........................................................................................................................ 82
2.10.1 TAS Instruction.................................................................................................... 82
2.10.2 STM/LDM Instruction......................................................................................... 82
Section 3 MCU Operating Modes .................................................................................. 83
3.1 Overview........................................................................................................................... 83
3.1.1 Operating Mode Selection ................................................................................... 83
3.1.2 Register Configuration......................................................................................... 84
3.2 Register Descriptions........................................................................................................84
3.2.1 Mode Control Register (MDCR) ......................................................................... 84
3.2.2 System Control Register (SYSCR)...................................................................... 85
3.2.3 Bus Control Register (BCR) ................................................................................ 87
3.2.4 Serial Timer Control Register (STCR) ................................................................ 88
3.3 Operating Mode Descriptions ........................................................................................... 89
3.3.1 Mode 1................................................................................................................. 89
3.3.2 Mode 2................................................................................................................. 89
3.3.3 Mode 3................................................................................................................. 90
3.4 Pin Functions in Each Operating Mode ............................................................................ 90
3.5 Memory Map in Each Operating Mode ............................................................................ 91
Section 4 Exception Handling ......................................................................................... 103
4.1 Overview........................................................................................................................... 103
4.1.1 Exception Handling Types and Priority............................................................... 103
4.1.2 Exception Handling Operation............................................................................. 104
4.1.3 Exception Sources and Vector Table................................................................... 104
4.2 Reset.................................................................................................................................. 106
4.2.1 Overview.............................................................................................................. 106
4.2.2 Reset Sequence .................................................................................................... 106
4.2.3 Interrupts after Reset............................................................................................ 108
4.3 Interrupts........................................................................................................................... 109
4.4 Trap Instruction................................................................................................................. 110
4.5 Stack Status after Exception Handling.............................................................................. 111
4.6 Notes on Use of the Stack................................................................................................. 112