Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 300 of 1130
REJ09B0327-0400
Table 10.3 Read and Write Access Methods for 16-Bit Registers
Read Write
Register Name Word Byte Word Byte
DADRA and DADRB Yes Yes Yes ×
DACNT Yes × Yes ×
Legend:
Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte
(first) and lower byte (second).
×: This type of access may give incorrect results.
CPU
(H'AA)
Upper byte
Bus
interface
Module data bus
Upper-Byte Write
TEMP
(H'AA)
DACNTL
( )
DACNTH
( )
CPU
(H'57)
Lower byte
Bus
interface
Module data bus
Lower-Byte Write
TEMP
(H'AA)
DACNTL
(H'57)
DACNTH
(H'AA)
Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)