Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 338 of 1130
REJ09B0327-0400
Address
Internal write signal
φ
OCRAR (OCRAF)
FRC
OCRA
N
The compare-match signal is inhibited and
automatic addition does not occur.
OCRAR(OCRAF) address
Old data New data
N N + 1
Compare-match
signal
Inhibited
Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Not Used)