Datasheet

Rev. 4.00 Sep 27, 2006 page xxxvii of xliv
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 601
18.5 Usage Note........................................................................................................................ 603
Section 19 D/A Converter................................................................................................. 605
19.1 Overview........................................................................................................................... 605
19.1.1 Features................................................................................................................ 605
19.1.2 Block Diagram..................................................................................................... 606
19.1.3 Input and Output Pins .......................................................................................... 607
19.1.4 Register Configuration......................................................................................... 607
19.2 Register Descriptions........................................................................................................ 608
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 608
19.2.2 D/A Control Register (DACR) ............................................................................ 608
19.2.3 Module Stop Control Register (MSTPCR).......................................................... 610
19.3 Operation .......................................................................................................................... 611
Section 20 A/D Converter................................................................................................. 613
20.1 Overview........................................................................................................................... 613
20.1.1 Features................................................................................................................ 613
20.1.2 Block Diagram..................................................................................................... 614
20.1.3 Pin Configuration................................................................................................. 615
20.1.4 Register Configuration......................................................................................... 616
20.2 Register Descriptions........................................................................................................ 616
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 616
20.2.2 A/D Control/Status Register (ADCSR) ............................................................... 617
20.2.3 A/D Control Register (ADCR) ............................................................................ 620
20.2.4 Keyboard Comparator Control Register (KBCOMP).......................................... 621
20.2.5 Module Stop Control Register (MSTPCR).......................................................... 622
20.3 Interface to Bus Master..................................................................................................... 623
20.4 Operation .......................................................................................................................... 624
20.4.1 Single Mode (SCAN = 0) .................................................................................... 624
20.4.2 Scan Mode (SCAN = 1)....................................................................................... 626
20.4.3 Input Sampling and A/D Conversion Time ......................................................... 628
20.4.4 External Trigger Input Timing............................................................................. 629
20.5 Interrupts........................................................................................................................... 629
20.6 Usage Notes ...................................................................................................................... 630
Section 21 RAM .................................................................................................................. 635
21.1 Overview........................................................................................................................... 635
21.1.1 Block Diagram..................................................................................................... 635
21.1.2 Register Configuration......................................................................................... 636
21.2 System Control Register (SYSCR) ................................................................................... 636