Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 365 of 1130
REJ09B0327-0400
φ
Clear signal
External reset
input pin
TCNT N H'00N – 1
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4 Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.8 shows the timing of this operation.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 12.8 Timing of OVF Setting
12.3.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer
mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare-
match count mode). In this case, the timer operates as described below.