Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 505 of 1130
REJ09B0327-0400
Bit 7
ICE Description
0I
2
C bus interface module disabled, with SCL and SDA signal pins set to port function
(Initial value)
I
2
C bus interface module internal states initialized
SAR and SARX can be accessed
1I
2
C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
Bit 6—I
2
C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I
2
C
bus interface to the CPU.
Bit 6
IEIC Description
0 Interrupts disabled (Initial value)
1 Interrupts enabled
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I
2
C bus interface operates in master mode or slave mode.
TRS selects whether the I
2
C bus interface operates in transmit mode or receive mode.
In master mode with the I
2
C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.