Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 529 of 1130
REJ09B0327-0400
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
Start condition
generation
SCL
(slave output)
Interrupt request
generation
Address + R/W
Address + R/W
[5] ICDR read [5] IRIC clear
User processing
Slave address
Data 1
[4]
A
R/W
Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0)