Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 557 of 1130
REJ09B0327-0400
SDA
SCL
A
TRS bit
Detection of 9th clock rise
(TRS = 1)
Address
8
RDRF bit
Start condition
12
A
3
Stop condition
ICDR read
TRS = 0 setting
Data
ICDRS data
full
Along with ICDRS: ICDRR transfer
Cancel condition of SCL =
Low fixation is set.
(3) TRS = 0
(2) RDRF = 0
(1) ICDRS data full
9
123456789
Figure 16.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
SDA
SCL
A
TRS bit
TRS = 0 setting
Address
89
8
9
TDRE bit
Start condition
12
A
3
Stop condition
ICDR write
Data
(2) TRS = 1
(1) TDRE = 0
4
Automatic TRS = 1 setting by
receiving R/W = 1
Along with ICDRS: ICDRR transfer
Cancel condition of SCL =
Low fixation
1234567
Figure 16.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode