Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 586 of 1130
REJ09B0327-0400
18.1.4 Register Configuration
Table 18.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 18.2 Host Interface Registers
R/W Master Address
*
4
Name
Abbrevia-
tion
Slave Host
Initial
Value
Slave
Address
*
3
CS1
CS1CS1
CS1 CS2
CS2CS2
CS2 CS3
CS3CS3
CS3 CS4
CS4CS4
CS4 HA0
System control register SYSCR R/W
*
1
— H'09 H'FFC4 — — ———
System control register 2 SYSCR2 R/W — H'00 H'FF83 — — ———
Host interface control
register 1
HICR R/W — H'F8 H'FFF0 — — ———
Host interface control
register 2
HICR2 R/W — H'F8 H'FE80 — — ———
Input data register 1 IDR1 R W — H'FFF4 0 1 110/1
*
5
Output data register 1 ODR1 R/W R — H'FFF5 01110
Status register 1 STR1 R/(W)
*
2
R H'00 H'FFF6 01111
Input data register 2 IDR2 R W — H'FFFC 10110/1
*
5
Output data register 2 ODR2 R/W R — H'FFFD 10110
Status register 2 STR2 R/(W)
*
2
RH'00H'FFFE 10111
Input data register 3 IDR3 R W — H'FE84 11010/1
*
5
Output data register 3 ODR3 R/W R — H'FE85 11010
Status register 3 STR3 R/(W)
*
2
RH'00H'FE86 11011
Input data register 4 IDR4 R W — H'FE8C 11100/1
*
5
Output data register 4 ODR4 R/W R — H'FE8D 11100
Status register 4 STR4 R/(W)
*
2
RH'00H'FE8E 11101
Module stop control MSTPCRH R/W — H'3F H'FF86 —————
register
MSTPCRLR/W — H'FFH'FF87 —————
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.