Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 588 of 1130
REJ09B0327-0400
Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface
registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2,
and STR2) can be accessed.
Bit 1
HIE Description
0 Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is disabled (Initial value)
1 Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is enabled
18.2.2 System Control Register 2 (SYSCR2)
Bit 76543210
KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E
Initial value00000000
Read/Write R/W R/W R/W — R/W R/W R/W R/W
SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface
functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can
be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2
is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be
set and changed by software. For details see section 8, I/O Ports.
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see
section 8, I/O Ports.
Bit 4—Reserved: Do not write 1 to this bit.