Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 591 of 1130
REJ09B0327-0400
HICR2
Bit 2
HICR2
Bit 1
HICR
Bit 2
HICR
Bit 1
IBFIE4 IBFIE3 IBFIE2 IBFIE1 Description
———0 Input data register (IDR1) reception completed interrupt
request disabled (Initial value)
———1 Input data register (IDR1) reception completed interrupt
request enabled
——0 — Input data register (IDR2) reception completed interrupt
request disabled (Initial value)
——1 — Input data register (IDR2) reception completed interrupt
request enabled
— 0 ——Input data register (IDR3) reception completed interrupt
request disabled (Initial value)
— 1 ——Input data register (IDR3) reception completed interrupt
request enabled
0 ———Input data register (IDR4) reception completed interrupt
request disabled (Initial value)
1 ———Input data register (IDR4) reception completed interrupt
request enabled
HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate
function. When the fast A20 gate is disabled, the normal A20 gate can be implemented byte
firmware operation of the P81 output.
HICR
Bit 0
FGA20E Description
0 Fast A20 gate function disabled (Initial value)
1 Fast A20 gate function enabled
HICR2 Bit 0—Reserved: Do not set this bit to 1.