Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 593 of 1130
REJ09B0327-0400
18.2.6 Status Register (STR)
Bit
Initial value
Slave Read/Write
Host Read/Write
Note: * Only 0 can be written, to clear the flag.
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)
*
R
2
DBU
0
R/W
R
1
IBF
0
R
R
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
STR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D
DD
D): Receives the HA0 input when the host processor writes to IDR1,
and indicates whether IDR1 contains data or a command.
Bit 3
C/D
DD
D Description
0 Contents of input data register (IDR1) are data (Initial value)
1 Contents of input data register (IDR1) are a command
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18.7.
Bit 1
IBF Description
0 [Clearing condition]
When the slave processor reads IDR (Initial value)
1 [Setting condition]
When the host processor writes to IDR