Datasheet

Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 703 of 1130
REJ09B0327-0400
n = N?
Yes
No
Yes
No
Set pins to boot mode and execute reset-start
n = 1
n + 1 → n
Host transfers data (H'00) continuously at prescribed
bit rate
The chip measures low period of H'00 data transmitted
by host
After bit rate adjustment, transmits one H'00 data byte
to host to indicate end of adjustment
Host confirms normal reception of bit rate adjustment
end indication (H'00), and transmits one H'55 data byte
After receiving H'55, trransmit one H'AA data byte
to host
Host transmits number of user program bytes (N),
upper byte followed by lower byte
The chip transmits received number of bytes to host as
verify data (echo-back)
Host transmits programming control program
sequentially in byte units
The chip transmits received programming control
program to host as verify data (echo-back)
Transfer received programming control program
to on-chip RAM
End of transmission
Check flash memory data, and if data has already
been written, erase all blocks
Check that all flash memory data has been erased
Check the starting ID code of the area to which the
programming control program is to be transferred
Execute programming control program transffered
to on-chip RAM
The chip transmits one H'AA data byte to the host
Start
The chip calculates bit rate and sets value in bit rate
register
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and
the erase operation and subsequent operations are halted.
ID code match?
The chip transmits one H'FF
data byte as an ID code error
and stops the subsequent
operations
Figure 23.8 Boot Mode Execution Procedure