Datasheet

Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 750 of 1130
REJ09B0327-0400
Bit 7
DTON Description
0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode
*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode (Initial value)
1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode
*
, or a transition is made to sleep mode
or software standby mode
When a SLEEP instruction is executed in subactive mode, a transition is made directly
to high-speed mode, or a transition is made to subsleep mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
Bit 6—Low-Speed On Flag (LSON): Determines the operating mode in combination with other
control bits when making a power-down transition by executing a SLEEP instruction. Also
controls whether a transition is made to high-speed mode or to subactive mode when watch mode
is cleared.
Bit 6
LSON Description
0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode
*
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode, or directly to high-speed mode
After watch mode is cleared, a transition is made to high-speed mode (Initial value)
1 When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode or subactive mode
*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode
After watch mode is cleared, a transition is made to subactive mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
Bit 5—Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which
the subclock (φSUB) input from the EXCL pin is sampled with the clock (φ) generated by the
system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0.