Datasheet

Rev. 3.00, 03/04, page 129 of 830
(3) 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be
inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Undefined
Write
High level
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
*
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)