Datasheet

Rev. 3.00, 03/04, page 415 of 830
Initialization
Read data from RDR and
clear RDRF flag in SSR to 0
Clear RE bit in SCR to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0
and PER = 0?
RDRF = 1 ?
All data received?
Yes
Figure 14.33 Sample Reception Flowchart
14.7.8 Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 14.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 14.34 Clock Output Fixing Timing