Datasheet
Rev. 3.00, 03/04, page 794 of 830
25.3.3 Bus Timing
Table 25.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.
Table 25.8 Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
15 ns
Address setup time t
AS
0.5 × t
cyc
–15
Figures 25.12 to 25.16
Address hold time t
AH
0.5 × t
cyc
–
10
CS delay time (IOS,
CS256, CPCS1)
t
CSD
15
AS delay time t
ASD
15
RD delay time 1 t
RSD1
15
RD delay time 2 t
RSD2
15
Read data setup time t
RDS
15
Read data hold time t
RDH
0
Read data access time 1 t
ACC1
1.0 × t
cyc
– 30
Read data access time 2 t
ACC2
1.5 × t
cyc
– 25
Read data access time 3 t
ACC3
2.0 × t
cyc
– 30
Read data access time 4 t
ACC4
2.5 × t
cyc
– 25
Read data access time 5 t
ACC5
3.0 × t
cyc
– 30
WR delay time 1 t
WRD1
15
WR delay time 2 t
WRD2
15
WR pulse width 1 t
WSW1
1.0 × t
cyc
–
20
WR pulse width 2 t
WSW2
1.5 × t
cyc
–
20
Write data delay time t
WDD
25
Write data setup time t
WDS
0
Write data hold time t
WDH
0.5 × t
cyc
– 5
WAIT setup time t
WTS
25
WAIT hold time t
WTH
5