To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. General Precautions on Handling of Product Configuration of This Manual Preface Main Revisions for This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7.
Preface This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 21, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.1 Overview 1 Table amended • On-chip memory H8S/2218 Group ROM Part No. ROM RAM Remarks Flash memory Version HD64F2218 128 kbytes 12 kbytes SCI boot mode HD64F2218U 128 kbytes 12 kbytes USB boot mode HD64F2218CU 128 kbytes 12 kbytes USB boot mode USB boot mode HD64F2217CU 64 kbytes 12 kbytes HD6432217 64 kbytes 8 kbytes ROM Part No.
Revision (See Manual for Details) 1.2 Internal Block Diagram 3 Title and figure amended Figure 1.1 Internal Block Diagram of HD64F2218, HD64F2218U, HD64F2218CU and HD642217CU EMLE* TDO* TCK* TMS* TRST* TDI* Page VCC VCC VSS VSS DrVCC DrVSS Item Boundary scan/H-UDI*2 Sub-clock pulse generator Main clock pulse generator MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLVSS OSC1 OSC2 STBY RES NMI FWE USPND/TMOW Interrupts controll Note *1 shown below deleted Notes: 1.
Item Page Revision (See Manual for Details) 1.2 Internal Block Diagram 6 Note amended 1. The FWE pin is provided only in the flash memory version. Figure 1.4 Internal Block Diagram of HD6432211, HD6432210 and HD6432210S Description amended The pin arrangements of the HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU are shown in figures 1.5 and 1.6. The pin arrangements of the HD6432217 are shown in figures 1.7 and 1.8.
Item Page Revision (See Manual for Details) Figure 1.6 Pin Arrangements of HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU (BP-112, BP-112V) 8 Title and figure amended A 11 10 B NC C D PD3/D11 PD0/D8 PE5/D5 PD5/D13 PD4/D12 PD2/D10 PE7/D7 9 FWE PD7/D15 NC PD1/D9 8 TDO* EMLE* NMI PD6/D14 7 TRST* TDI* TMS* TCK* 6 PF7/φ VSS VCC PF6/AS Note *1 shown below deleted Notes: 1. The FWE pin is provided only in the HD64F2218, andHD64F2218U. Figure 1.
Item Page Revision (See Manual for Details) 1.3 Pin Arrangement 12 Note amended 1. The FWE pin is provided only in the flash memory version. Figure 1.11 Pin 13 Arrangements of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU (TNP-64B, TNP-64BV) Title and figure amended PE7 Figure 1.10 Pin Arrangements of HD6432211, HD6432210 and HD6432210S (FP64E, FP-64EV) 48 FWE NMI EMLE* TDO/P77* TCK/P76* TMS/P75* TRST/NC* TDI/PG0* VCC Note *1 shown below deleted Notes: 1.
Item Page 3.4 Memory Map in 77 Each Operating Mode Revision (See Manual for Details) Title amended Figure 3.1 Memory Map in Each Operating Mode for HD64F2218, HD64F2218U and HD64F2218CU Figure 3.2 Memory Map in Each Operating Mode for HD64F2217CU 78 Figure added Figure 3.4 Memory Map in Each Operating Mode for HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU, HD64F2210CU, HD6432211, HD6432210 and HD6432210S 80 Figure replaced 4.
Item Page Revision (See Manual for Details) 12.3.
Item Page Revision (See Manual for Details) 12.3.11 Bit Rate Register (BRR) 401 Table amended Operating Frequency • Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate Figure 12.6 Receive Data Sampling Timing in Asynchronous Mode Section 13 Boundary 449 Scan Function 24 (bps ) n N n 110 3 70 — ...... 250 2 124 2 ...... 500 1 249 2 — — 1k 1 124 1 ...... — — 2.5 k 0 199 1 ...... 2 149 5k 0 99 0 ...... 2 74 10 k 0 49 0 ......
Item Page Revision (See Manual for Details) 13.3.2 IDCODE Register (IDCODE) 454 Description amended ...The HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU output fixed codes H'002A200F from the TDO. ... Table 13.3 IDCODE Register Configuration Table amended Bits HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU codes Contents 14.3.
Item Page Revision (See Manual for Details) Section 16 RAM 551 Table amended Product Class H8S/2218 Group HD64F2218 ROM Type RAM Size Flash memory Version 12 kbytes RAM Address H'FFC000 to H'FFEFBF H'FFFFC0 to H'FFFFFF HD64F2218U HD64F2218CU HD64F2217CU HD6432217 Masked ROM Version 8 kbytes H'FFD000 to H'FFEFBF HDF64F2212 Flash memory Version 12 kbytes H'FFC000 to H'FFEFBF H'FFFFC0 to H'FFFFFF H8S/2212 Group H'FFFFC0 to H'FFFFFF HDF64F2212U HDF64F2212CU 8 kbytes HD64F2211 H'FFD000 to
Item Page Revision (See Manual for Details) 17.1 Features 554 Note amended Figure 17.1 Block Diagram of Flash Memory 17.3 Block Configuration Note: * 128 kbytes in the HD64F2218, HD64F2218U, HD64F2218CU, HD64F2212, HD64F2212U and HD64F2212CU; 64 kbytes in the HD64F2217CU, HD64F2211, HD64F2211U and HD64F2211CU. 32 kbytes in the HD64F2210CU 558 Description amended Figure 17.
Item Page Revision (See Manual for Details) 17.6 On-Board Programming Modes 567 Table amended Mode Table 17.3 Setting On-Board Programming Modes SCI boot mode (HD64F2218, HD64F2212, HD64F2211) USB boot mode (HD64F2218U, HD64F2218CU, HD64F2217CU, HD64F2212U, HD64F2212CU, HD64F2211U, HD64F2211CU, HD64F2210CU) 17.6.1 SCI Boot Mode 569 (HD64F2218, HD64F2212, and HD64F2211) 17.6.2 USB Boot Mode (HD64F2218U, HD64F2212U, and HD64F2211U) 573 Description amended 5.
Item Page 22.2 Power Supply 658 Voltage and Operating Frequency Range Figure 22.1 Power Supply Voltage and Operating Ranges Revision (See Manual for Details) Figure amended (1) Mask ROM versions (except for HD6432210S) Frequency f System clock 24 MHz 16 MHz 6 MHz Sub clock 32.768 kHz 0 2.4 2.7 3.6 3.0 Power ssupply voltage Vcc, PLLVcc, DrVcc (V) (2) Masked ROM version (HD6432210S) Frequency f System clock 24 MHz 16 MHz 6 MHz Condition A: Vcc = PLLVcc = DrVcc = 2.4 to 3.6V Vref = 2.
Item Page Revision (See Manual for Details) B. Product Model Lineup 689 to 690 Table amended Product Class H8S/2218 Group Flash memory Version Part No.
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1.4 1.5 1 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 3 Pin Arrangements...........................................................................
2.8 2.9 Processing States ............................................................................................................... Usage Notes....................................................................................................................... 2.9.1 Note on TAS Instruction Usage ........................................................................... 2.9.2 STM/LTM Instruction Usage ............................................................................... 2.9.
5.4 5.5 5.6 5.7 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.3.4 IRQ Status Register (ISR).................................................................................... Interrupt Sources ............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts......
6.6.2 Valid Strobes ........................................................................................................ 135 6.6.3 Basic Timing ........................................................................................................ 136 6.6.4 Wait Control......................................................................................................... 145 6.7 Burst ROM Interface .......................................................................................................
7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 DMAC Register Access during Operation........................................................... Module Stop......................................................................................................... Medium-Speed Mode........................................................................................... Activation Source Acceptance ............................................................................. Internal Interrupt after End of Transfer.....
8.8 8.9 8.10 8.11 8.12 8.13 8.7.3 Port B Register (PORTB)..................................................................................... 240 8.7.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 241 8.7.5 Pin Functions........................................................................................................ 242 8.7.6 Port B Input Pull-Up MOS States ........................................................................
9.3 9.4 9.5 9.6 9.7 9.8 Register Descriptions ........................................................................................................ 9.3.1 Timer Control Register (TCR) ............................................................................. 9.3.2 Timer Mode Register (TMDR) ............................................................................ 9.3.3 Timer I/O Control Register (TIOR) ..................................................................... 9.3.
10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 Notes on Register Access ..................................................................................... 346 Contention between Timer Counter (TCNT) Write and Increment...................... 347 Changing Value of CKS2 to CKS0 ...................................................................... 348 Switching between Watchdog Timer Mode and Interval Timer Mode ................ 348 Internal Reset in Watchdog Timer Mode .........................................
12.3.11 Bit Rate Register (BRR) ...................................................................................... 12.4 Operation in Asynchronous Mode .................................................................................... 12.4.1 Data Transfer Format ........................................................................................... 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 12.4.3 Clock..............................................................
Section 13 Boundary Scan Function .............................................................................. 449 13.1 Features ............................................................................................................................. 449 13.2 Pin Configuration .............................................................................................................. 451 13.3 Register Descriptions.......................................................................................
14.4 14.5 14.6 14.7 14.8 14.3.26 USB Configuration Value Register (UCVR) ....................................................... 14.3.27 USB Test Register 0 (UTSTR0) .......................................................................... 14.3.28 USB Test Register 1 (UTSTR1) .......................................................................... 14.3.29 USB Test Registers 2 and A to F (UTSTR2, UTSTRA to UTSTRF).................. 14.3.30 Module Stop Control Register B (MSTPCRB).......................
15.2 Input/Output Pins .............................................................................................................. 537 15.3 Register Descriptions......................................................................................................... 537 15.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 538 15.3.2 A/D Control/Status Register (ADCSR)................................................................ 538 15.3.
17.8.2 Erase/Erase-Verify............................................................................................... 17.9 Program/Erase Protection.................................................................................................. 17.9.1 Hardware Protection ............................................................................................ 17.9.2 Software Protection.............................................................................................. 17.9.
20.3 Sleep Mode........................................................................................................................ 618 20.3.1 Transition to Sleep Mode ..................................................................................... 618 20.3.2 Exiting Sleep Mode .............................................................................................. 618 20.4 Software Standby Mode ..................................................................................................
Section 22 Electrical Characteristics.............................................................................. 657 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Absolute Maximum Ratings ............................................................................................. Power Supply Voltage and Operating Frequency Range .................................................. DC Characteristics ............................................................................................................
Rev.7.00 Dec.
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of HD64F2218, HD64F2218U, HD64F2218CU and HD642217CU......................................................................................................... Figure 1.2 Internal Block Diagram of HD6432217 ................................................................. Figure 1.3 Internal Block Diagram of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU....................... Figure 1.
Section 3 MCU Operating Modes Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Memory Map in Each Operating Mode for HD64F2218, HD64F2218U and HD64F2218CU....................................................................................................... Memory Map in Each Operating Mode for HD64F2217CU .................................. Memory Map in Each Operating Mode for HD6432217........................................
Figure 6.14 Figure 6.15 Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20 Figure 6.21 Figure 6.22 Figure 6.23 Figure 6.24 Figure 6.25 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) ...... Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)........................... Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) ..... Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) ......
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 9.16 Figure 9.17 Figure 9.18 Figure 9.19 Figure 9.20 Figure 9.21 Figure 9.22 Figure 9.23 Figure 9.24 Figure 9.25 Figure 9.26 Figure 9.27 Figure 9.28 Figure 9.29 Figure 9.30 Figure 9.31 Figure 9.32 Figure 9.33 Figure 9.34 Figure 9.35 Figure 9.36 Figure 9.37 Figure 9.38 Figure 9.39 Figure 9.
Figure 9.41 Figure 9.42 Figure 9.43 Figure 9.44 Figure 9.45 Figure 9.46 Figure 9.47 Figure 9.48 Figure 9.49 Figure 9.50 Figure 9.51 Figure 9.52 Figure 9.53 TCIU Interrupt Setting Timing............................................................................... Timing for Status Flag Clearing by CPU ............................................................... Timing for Status Flag Clearing by DMAC Activation .........................................
Figure 12.4 Example of Average Transfer Rate Setting when TPU Clock Is Input (4)............ 394 Figure 12.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 403 Figure 12.6 Receive Data Sampling Timing in Asynchronous Mode........................................ 405 Figure 12.7 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) ..............................................................
Figure 12.35 Clock Halt and Restart Procedure .......................................................................... Figure 12.36 Example of Communication Using the SCI Select Function ................................. Figure 12.37 Example of Communication Using the SCI Select Function ................................. Figure 12.38 Example of Clocked Synchronous Transmission by DMAC ................................. Figure 12.39 Sample Flowchart for Mode Transition during Transmission...................
Figure 14.18 EP1 Bulk-In Transfer Operation............................................................................. 514 Figure 14.19 EP2 Bulk-Out Transfer Operation .......................................................................... 515 Figure 14.20 Forcible Stall by Firmware ..................................................................................... 518 Figure 14.21 Automatic Stall by USB Function Module ............................................................. 519 Figure 14.
Figure 17.13 Program/Program-Verify Flowchart....................................................................... Figure 17.14 Erase/Erase-Verify Flowchart ................................................................................ Figure 17.15 Memory Map in Programmer Mode....................................................................... Figure 17.16 Power-On/Off Timing (Boot Mode)....................................................................... Figure 17.
Figure 22.7 Basic Bus Timing (Two-State Access) ................................................................... 670 Figure 22.8 Basic Bus Timing (Three-State Access) ................................................................. 671 Figure 22.9 Basic Bus Timing (Three-State Access with One Wait State)................................ 672 Figure 22.10 Burst ROM Access Timing (Two-State Access) .................................................... 673 Figure 22.11 External Bus Release Timing ............
Tables Section 1 Table 1.1 Table 1.2 Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Section 3 Table 3.1 Table 3.2 Section 4 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Section 5 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Overview Pin Functions in Each Operating Mode for H8S/2218 Group................................ 15 Pin Functions in Each Operating Mode for H8S/2212 Group...........
Section 6 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Section 7 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Bus Controller Pin Configuration.....................................................................................
Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Table 8.35 Table 8.36 Table 8.37 Table 8.38 Table 8.39 Table 8.40 Table 8.41 Table 8.42 Table 8.43 Table 8.44 Table 8.45 Table 8.46 Table 8.47 Table 8.48 Table 8.49 Table 8.50 Table 8.51 Table 8.52 Table 8.53 Table 8.54 Table 8.55 Table 8.56 Table 8.57 Table 8.58 Table 8.59 Table 8.60 Table 8.61 P31 Pin Function ...........................................
Table 8.62 Table 8.63 Table 8.64 Table 8.65 Table 8.66 Table 8.67 Table 8.68 Table 8.69 Table 8.70 Table 8.71 Table 8.72 Table 8.73 Table 8.74 Table 8.75 Table 8.76 Table 8.77 Table 8.78 Table 8.79 Table 8.80 Table 8.81 Table 8.82 Table 8.83 Table 8.84 Table 8.85 Table 8.86 Table 8.87 Table 8.88 Table 8.89 Table 8.90 Table 8.91 Table 8.92 Table 8.93 Table 8.94 Table 8.95 Table 8.96 Table 8.97 Table 8.98 Section 9 Table 9.1 Table 9.2 PD0 Pin Function.........................................................
Table 9.3 Table 9.4 Table 9.5 Table 9.6 Table 9.7 Table 9.8 Table 9.9 Table 9.10 Table 9.11 Table 9.12 Table 9.13 Table 9.14 Table 9.15 Table 9.16 Table 9.17 Table 9.18 Table 9.19 Table 9.20 Table 9.21 Table 9.22 Table 9.23 Table 9.24 CCLR2 to CCLR0 (channel 0) ............................................................................... CCLR2 to CCLR0 (channels 1 and 2).................................................................... TPSC2 to TPSC0 (channel 0).........................................
Table 12.9 Table 12.10 Table 12.11 Table 12.12 Table 12.13 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)............. 402 Serial Transfer Formats (Asynchronous Mode)...................................................... 404 SSR Status Flags and Receive Data Handling ........................................................ 411 SCI Interrupt Sources .............................................................................................
Table 19.2 Table 19.3 Table 19.4 Crystal Resonator Characteristics........................................................................... 600 External Clock Input Conditions ............................................................................ 601 External Clock Input Conditions when Duty Adjustment Circuit Is not Used....... 602 Section 20 Power-Down Modes Table 20.1 Table 20.2 Table 20.3 Table 20.4 LSI Internal States in Each Mode..............................................................
Rev.7.00 Dec.
Section 1 Overview Section 1 Overview 1.
Section 1 Overview H8S/2212 Group ROM Part No.
Section 1 Overview 1.2 Internal Block Diagram PE7 /D7 PE6 /D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 EMLE* TDO* TCK* TMS* TRST* TDI* VCC VCC VSS VSS DrVCC DrVSS The internal block diagram of the HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU is shown in figure 1.1. The internal block diagram of the HD6432217 is shown in figure 1.2.
PE7 /D7 PE6 /D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 USB WDT ROM PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 / A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 SCI0 (High speed UART) Port 3 Port F RAM Peripheral address bus Bus controller Peripheral data bus Internal data bus DMAC SCI2 RTC P36 (PUPD+) P32/ SCK0/IRQ4 P31/ RxD0 P30/ TxD0 A
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 EMLE* TDO/P77* TCK/P76* TMS/P75* TRST/NC* TDI/PG0* VCC VCC VSS VSS DrVCC DrVSS Section 1 Overview Port E H-UDI/ports 7 and G* Bus controller PA3 /SCK2 PA2 /RxD2 PA1 /TxD2 USB WDT ROM Peripheral address bus DMAC Peripheral data bus Interrupts controller Internal data bus Sub-clock pulse generator STBY RES NMI FWE USPND/TMOW USD+ USDUBPM VBUS RAM Port F SCI0 (High speed UART) Port 3 PF7 / φ PF3 /ADTRG/IRQ3 PF0 /IRQ2 H8S/2000 CPU Internal address bus Main c
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 NC*2 P77*2 P76*2 P75*2 NC*2 PG0*2 VCC VCC VSS VSS DrVCC DrVSS Section 1 Overview Port E Ports 7 and G*2 Bus controller PA3 /SCK2 PA2 /RxD2 PA1 /TxD2 USB WDT ROM Peripheral address bus DMAC Peripheral data bus Interrupts controller Internal data bus Sub-clock pulse generator STBY RES NMI FWE*1 USPND/TMOW USD+ USDUBPM VBUS RAM Port F SCI0 (High speed UART) Port 3 PF7 / φ PF3 /ADTRG/IRQ3 PF0 /IRQ2 H8S/2000 CPU Internal address bus Main clock pulse generator
Section 1 Overview 1.
Section 1 Overview A 11 10 B C D F G H J K L PD3/D11 PD0/D8 PE5/D5 PE2/D2 P70/CS4 XTAL STBY OSC1 PB7/A15 NC PD5/D13 PD4/D12 PD2/D10 PE7/D7 PE3/D3 PE0/D0 EXTAL P71/CS5 OSC2 PB6/A14 PB5/A13 NC PD1/D9 PE4/D4 VCC VSS P74/ MRES NC PB4/A12 UBPM NMI PD6/D14 PE6/D6 PE1/D1 RES NC PLLVCC PLLVSS P41/AN1 NC 9 FWE 8 TDO 7 TRST * TDI* TMS* TCK* 6 PF7/φ VSS VCC PF6/AS 5 E * PD7/D15 EMLE * P40/AN0 P42/AN2 P43/AN3 BP-112 BP-112V (Top view) Vref PB1/A9
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TFP-100G TFP-100GV (Top View) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PB5/A13 PB4/A12 PLLVCC UBPM PLLVSS P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref PB3/A11 PB2/A10 PB1/A9 PB0/A8 P96/AN14 P97/AN15 DrVSS USDUSD+ DrVCC P36(PUPD+) VBUS PG4/CS0 PG3/CS1 PG2/CS2 PA0/A16 P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD P
Section 1 Overview A 11 10 C D E F G H J K L PD3/D11 PD0/D8 PE5/D5 PE2/D2 P70/CS4 XTAL STBY OSC1 PB7/A15 NC PD5/D13 PD4/D12 PD2/D10 PE7/D7 PE3/D3 PE0/D0 EXTAL P71/CS5 OSC2 PB6/A14 PB5/A13 PD7/D15 NC PD1/D9 PE4/D4 VCC VSS P74/ MRES NC PB4/A12 UBPM NC*2 NMI PD6/D14 PE6/D6 PE1/D1 RES NC PLLVCC PLLVSS P41/AN1 NC *1 9 FWE 8 NC 7 NC 6 PF7/φ 5 B *2 *2 NC *2 VSS NC *2 VCC NC *2 P40/AN0 P42/AN2 P43/AN3 BP-112 BP-112V (Top view) PF6/AS Vref P
OSC2 OSC1 STBY RES VSS XTAL EXTAL VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FWE 49 32 PLLVCC NMI 50 31 UBPM EMLE* 51 30 PLLVSS TDO/P77* 52 29 P40/AN0 TCK/P76* 53 28 P41/AN1 TMS/P75* 54 27 P42/AN2 TRST/NC* 55 26 P43/AN3 TDI/PG0* 56 25 Vref VCC 57 24 P96/AN14 PF7/φ 58 23 P97/AN15 VSS 59 22 DrVSS PF3/ADTRG/IRQ3 60 21 USD- PF0/IRQ2 61 20 USD+ PA3/SCK2 62 19 DrVCC PA2/RXD2 63 18
OSC2 OSC1 STBY RES VSS XTAL EXTAL VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FWE*1 49 32 PLLVCC NMI 50 31 UBPM NC*2 51 30 PLLVSS P77*2 52 29 P40/AN0 P76*2 53 28 P41/AN1 P75*2 54 27 P42/AN2 NC*2 55 26 P43/AN3 PG0*2 56 25 Vref VCC 57 24 P96/AN14 PF7/φ 58 23 P97/AN15 VSS 59 22 DrVSS PF3/ADTRG/IRQ3 60 21 USD- PF0/IRQ2 61 20 USD+ PA3/SCK2 62 19 DrVCC PA2/RXD2 63 18 P36 (PUPD+)
OSC2 OSC1 STBY RES VSS XTAL EXTAL VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FWE 49 32 PLLVCC NMI 50 31 UBPM EMLE* 51 30 PLLVSS TDO/P77* 52 29 P40/AN0 TCK/P76* 53 28 P41/AN1 TMS/P75* 54 27 P42/AN2 TRST/NC* 55 26 P43/AN3 TDI/PG0* 56 25 Vref VCC 57 24 P96/AN14 PF7/φ 58 23 P97/AN15 VSS 59 22 DrVSS PF3/ADTRG/IRQ3 60 21 USD- PF0/IRQ2 61 20 USD+ PA3/SCK2 62 19 DrVCC PA2/RXD2 63 18
OSC2 OSC1 STBY RES VSS XTAL EXTAL VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FWE*1 49 32 PLLVCC NMI 50 31 UBPM NC*2 51 30 PLLVSS P77*2 52 29 P40/AN0 P76*2 53 28 P41/AN1 P75*2 54 27 P42/AN2 NC*2 55 26 P43/AN3 PG0*2 56 25 Vref VCC 57 24 P96/AN14 PF7/φ 58 23 P97/AN15 VSS 59 22 DrVSS PF3/ADTRG/IRQ3 60 21 USD- PF0/IRQ2 61 20 USD+ PA3/SCK2 62 19 DrVCC PA2/RXD2 63 18 P36 (PUPD+)
Section 1 Overview 1.4 Pin Functions in Each Operating Mode Table 1.1 shows the pin functions in each operating mode for the H8S/2218 Group, and table 1.2 shows that for the H8S/2212 Group. Table 1.1 Pin Functions in Each Operating Mode for H8S/2218 Group Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview 1.5 Pin Functions Pin No. Type Symbol TFP-100G, BP-112, TFP-100GV BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV Power supply VCC 62 F9 40 88 C6 57 59 G9 37 90 B6 59 PLLVCC 48 J8 32 Input Power supply pin for an on-chip PLL oscillator. Connect this pin to the system power supply. PLLVSS 46 K8 30 Input Ground pin for an on-chip PLL oscillator XTAL 60 G11 38 Input For connection to a crystal resonator.
Section 1 Overview Pin No. Type Symbol TFP-100G, BP-112, TFP-100GV BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV System control RES* 58 G8 36 Input Reset pin. When this pin is driven low, the chip is reset. STBY* 57 H11 35 Input When this pin is driven low, a transition is made to hardware standby mode. MRES 55 H9 ⎯ Input When this pin is driven low, a transition is made to manual reset mode.
Section 1 Overview Pin No. TFP-100G, BP-112, TFP-100GV BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV I/O Function Address bus A23 5 C1 ⎯ Output A22 4 C2 ⎯ A21 3 D4 ⎯ These pins output an address.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Type Symbol TFP-100G, BP-112, TFP-100GV BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV Bus control HWR 93 B5 ⎯ Output A strobe signal that writes to external address space and indicates that the upper half (D15 to D8) of the data bus is enabled. (Supported only by the H8S/2218 Group) LWR 94 C5 ⎯ Output A strobe signal that writes to external address space and indicates that the lower half (D7 to D0) of the data bus is enabled.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Type Symbol TFP-100G, BP-112, TFP-100GV BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV USB USD+* 32 K4 20 USD-* 33 L4 21 VBUS* 29 K3 17 Input Connection/disconnection detecting input pin for the USB cable USPND 21 G4 12 Output USB suspend output I/O Function I/O USB data I/O pin This pin is driven high when a transition is made to suspend state.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Rev.7.00 Dec.
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states ⎯ 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * Normal mode is not available in this LSI. • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed selection 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Extended address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space A maximum address space of 64 kbytes can be accessed.
Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1 *3 ( SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. 2. 3. (b) Exception Handling When EXR is not used, it is not stored on the stack. SP when EXR is not used.
Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 H'00000000 64 kbytes H'FFFF 16 Mbytes H'00FFFFFF Data area Not available in this LSI.
Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Section 2 CPU Bit Bit Name Initial Value R/W Description 1 V undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a carry • Shift and rotate instructions, to indicate a carry They carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.
Section 2 CPU Data Type Register Number Data Image 7 0 1-bit data RnH 7 6 5 4 3 2 1 0 1-bit data RnL Don't care 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Don't care 7 7 4 3 Upper 0 7 6 5 4 3 2 1 0 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data 0 Lower RnL 0 Don't care MSB LSB Figure 2.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size*1 Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions Instruction Size*1 Function ADD Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L SUB ADDX Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU 1 Instruction Size* Function NEG 0 – Rd → Rd B/W/L Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.
Section 2 CPU Table 2.6 Shift Instructions Instruction Size* Function SHAL Rd (shift) → Rd B/W/L SHAR SHLL Performs an arithmetic shift on general register contents. 1-bit or 2 bit shift is possible. B/W/L SHLR ROTL B/W/L ROTR ROTXL ROTXR Rd (shift) → Rd Performs an logical shift on general register contents. 1-bit or 2 bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2 bit rotation is possible.
Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET 1 → ( of ) B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ (
Section 2 CPU Instruction Size* Function BXOR C ⊕ ( of ) → C B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instruction Instruction Size* Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instruction Instruction Size Function EEPMOV.B – if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W – if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfer a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev.7.00 Dec.
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect.
Section 2 CPU 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address H'000000 to H'FFFFFF 24 bits (@aa:24) Note: * Not available in this LSI. 2.7.
Section 2 CPU 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long.
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Section 2 CPU No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state the CPU and internal peripheral modules are all initialized and stop. When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request Program execution state ha nd lin g SLEEP instruction, SSBY = 0 ep tio n s bu t of est d es qu En requ e r s Bu Sleep mode tf Re qu es En d o ha f ex nd ce lin pti g o n or e xc Bus-released state Exception handling state RES = High MRES = High qu t re rup r Inte est SLEEP instruction, SSBY = 1 External interrupt request Software standby mode STBY = High, RES = Low Reset state*1 Hardware standby mode*2 Power-down state*3 Notes: 1.
Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.9.
Section 2 CPU The instructions BSET, BCLR, BNOT, BST, and BIST perform the following operations in the order shown: 1. Read data in byte units 2. Perform bit manipulation on the read data according to the instruction 3. Write data in byte units Example: Using the BCLR instruction to clear pin 14 only of P1DDR for port 1 P1DDR is an 8-bit register that contains write-only bits. It is used to specify the I/O setting of the individual pins in port 1. Reading produces invalid data.
Section 2 CPU P17 P16 P15 P14 P13 P12 P11 P10 I/O Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 Read value 1 1 1 1 1 0 0 0 The BCLR instruction performs bit manipulation on the read value, which is H'F8 in this example. It clears bit 4 to 0.
Section 2 CPU In order to write to a register containing write-only bits, set aside a work area in memory (in onchip RAM, for example) and write the data to be manipulated to it. After accessing and manipulating the data in the work area in memory, write the resulting data to the register containing write-only bits. Figure 2.
Section 2 CPU P17 P16 P15 P14 P13 P12 P11 P10 I/O Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 RAM0 1 1 1 1 0 0 0 0 To change pin 14 from an output pin to an input pin, the value of bit 4 in P1DDR must be changed from 1 to 0 (H'F0 to H'E0). Here the BCLR instruction will be used to clear bit 4 in P1DDR to 0.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0) as show in table 3.1. Modes 4 to 6 are external extended modes that allow access to the external memory and peripheral devices.
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode of this LSI. MDCR should not be modified. Bit Bit Name Initial Value R/W 7 to 4 ⎯ Undefined ⎯ Description Reserved These bits are always read as undefined value and cannot be modified.
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 7 – 0 R/W Reserved 6 – 0 – The write value should always be 0. Reserved This bit is always read as 0 and cannot be modified. 5 INTM1 0 R/W 4 INTM0 0 R/W These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation.
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 (Supported Only by the H8S/2218 Group) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset.
Section 3 MCU Operating Modes 3.3.3 Mode 6 (Supported Only by the H8S/2218 Group) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B and C function as input ports immediately after a reset. Address (A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values.
Section 3 MCU Operating Modes 3.3.5 Pin Functions The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.4 show the memory map in each operation mode, respectively.
Section 3 MCU Operating Modes ROM: ⎯ RAM: 12 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM desabled) H'000000 ROM: 64 kbytes RAM: 12 kbytes Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 ROM: 64 kbytes RAM: 12 kbytes Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 H'00FFFF Reserved H'020000 External address space External address space H'C00000 H'C00000 USB registers*1 USB registers*1 H'E00000 H'FEE800 External address space
Section 3 MCU Operating Modes ROM: ⎯ RAM: 8 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM desabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 H'00FFFF Reserved H'020000 External address space External address space H'C00000 H'C00000 USB registers*1 USB registers*1 H'E00000 H'FEE800 External address space Re
Section 3 MCU Operating Modes HD64F2212, HD64F2212U, HD64F2212CU ROM: 128 kbytes RAM: 12 kbytes HD64F2211, HD64F2211U, HD64F2211CU,HD6432211 ROM: 64 kbytes RAM: 8 kbytes HD64F2210CU ROM: 32 kbytes RAM: 8 kbytes HD6432210, HD6432210S ROM: 32 kbytes RAM: 4 kbytes Mode 7 (advanced single-chip mode) Mode 7 (advanced single-chip mode) Mode 7 (advanced single-chip mode) Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM H'00FFFF USB registers H'C00000 H'DFFFFF H'000000 On-chip ROM H'0
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES or MRES* pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up or hold the RES or MRES* pin low for at least 20 states during operation. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by overflow of the watchdog timer.
Section 4 Exception Handling Table 4.3 Reset Types Reset Transition Condition Internal State Type MRES RES CPU On-Chip Peripheral Modules Power-on reset × Low Initialized Initialized Manual reset Low High Initialized Initialized, except for bus controller and I/O ports Legend: ×: Don't care A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset.
Section 4 Exception Handling Internal Prefetch of first processing program instruction Vector fetch * * * φ RES, MRES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (1) (3) (2) (4) (5) (6) (2) (4) (6) Reset exception handling vector address (for power-on reset, (1) = H'000000, (3) = H'000002; for manual reset, (1) = H'000004, (3) = H'000006) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * Three progra
Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction φ RES, MRES Internal Address bus (1) (3) (5) Internal read signal Internal write signal High Internal data bus (2) (4) (6) (1) (3) : Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002 for a manual reset, (1) = H'000004, (3) = H'000006) (2) (4) : Start address (contents of reset exceptiion handling vector address) (5) : Start address ((5) = (2) (4)) (6
Section 4 Exception Handling 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.
Section 4 Exception Handling 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared. 3.
Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1. Ignored on return. 2.
Section 4 Exception Handling 4.8 Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times.
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR IER Interrupt request Vector number Priority determination I Internal interrupt request WOVI to EXIRQ1 CCR I2 to I0 IPR Interrupt controller Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected IRQ7 Input Maskable external interrupts IRQ4 Input IRQ3 Input IRQ2 Input Rising, falling, or both edges, or level sensing can be selected (IRQ6 is an interrupt signal only for the on-chip USB. IRQ5 is an interrupt signal only for the on-chip RTC.
Section 5 Interrupt Controller 5.3.1 Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM) The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in section 5.5, Interrupt Exception Handling Vector Table. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Section 5 Interrupt Controller 5.3.2 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 7 IRQ7E 0 IRQ7 Enable R/W The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable*1 The IRQ6 interrupt request is enabled when this bit is 1. 5 IRQ5E 0 R/W IRQ5 Enable*2 The IRQ5 interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA 0 R/W IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5 IRQ2SCB 0 R/W IRQ2 Sense Control B 4 IRQ2SCA 0 R/W IRQ2 Sense Control A 00: Inter
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA 0 R/W IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Legend: ×: Don’t care Notes: 1. IRQ6 is an interrupt only for the on-chip USB. 2.
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are seven external interrupts: NMI, IRQ7, and IRQ4 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. Though IRQ5 is only for the on-chip RTC and IRQ6 is only for the on-chip USB, the interrupts can be used to restore this LSI from software standby mode. IRQ5 and IRQ6 are functionally same as IRQ7 and IRQ4 to IRQ0.
Section 5 Interrupt Controller The set timing for IRQnF is shown in figure 5.3. φ IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Timing of Setting IRQnF The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function.
Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.
Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector Number TPU channel 2 TGI2A DMAC SCI channel 0 SCI channel 2 USB Vector Address* Advanced Mode IPR Priority 44 H'00B0 IPRG6 to IPRG4 High TGI2B 45 H'00B4 TGI2V 46 H'00B8 TGI2U 47 H'00BC DEND0A 72 H'0120 DEND0B 73 H'0124 DEND1A 74 H'0128 DEND1B 75 H'012C ERI0 80 H'0140 RXI0 81 H'0144 TXI0 82 H'0148 TEI0 83 H'014C ERI2 88 H'0160 RXI2 89 H'0164 TXI2 90 H'0168 TEI2 91 H'01
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 No Yes IRQ1 Yes EXIRQ1 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? No Level 6 interrupt? No Yes Level 1 interrupt? Yes Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.7.00 Dec.
(2) (4) (3) (5) (7) (1) (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times ⎯ the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.
Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16-Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6 + 2m 2 3+m Legend: m: Number of wait states in an external device access. 5.6.5 DMAC Activation by Interrupt The DMAC can be activated by an interrupt.
Section 5 Interrupt Controller DMAC Disenable signal IRQ interrupt On-chip peripheral module Interrupt request Clear signal Selection circuit Interrupt source clear signal Control logic Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5.7 Interrupt Control for DMAC Selection of Interrupt Source: An activation factor is directly input to each channel of the DMAC.
Section 5 Interrupt Controller Table 5.6 Interrupt Source Selection and Clearing Control Settings DMAC Interrupt Sources Selection/Clearing Control DTA DMAC CPU 0 Δ Ο 1 Ο X Legend: Ο: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) Δ: The relevant interrupt is used. The interrupt source is not cleared. X: The relevant bit cannot be used.
Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
Section 5 Interrupt Controller 5.7.6 NMI Interrupt Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. No operations, including NMI interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the LSI’s pins.
Section 6 Bus Controller Section 6 Bus Controller This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and DMA controller (DMAC). 6.
Section 6 Bus Controller Figure 6.1 shows a block diagram of the bus controller.
Section 6 Bus Controller 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. These pins are supported only by the H8S/2218 Group. Table 6.1 Pin Configuration Name Symbol I/O Function Address strove AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read.
Section 6 Bus Controller 6.3 Register Descriptions The following shows the registers of the bus controller. • • • • • • • Bus width control register (ABWCR) Access state control register (ASTCR) Wait control register H (WCRH) Wait control register L (WCRL) Bus control register H (BCRH) Bus control register L (BCRL ) Pin function control register (PFCR) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area for either 8-bit access or 16-bit access.
Section 6 Bus Controller 6.3.2 Access State Control Register (ASTCR) ASTCR designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless of the settings in ASTCR.
Section 6 Bus Controller 6.3.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers except for the on-chip USB.
Section 6 Bus Controller Bit Bit Name Initial Value R/W Description 3 W51 1 R/W Area 5 Wait Control 1 and 0 2 W50 1 R/W These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Section 6 Bus Controller • WCRL Bit Bit Name Initial Value R/W Description 7 W31 1 R/W Area 3 Wait Control 1 and 0 6 W30 1 R/W These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Section 6 Bus Controller Bit Bit Name Initial Value R/W Description 3 W11 1 R/W Area 1 Wait Control 1 and 0 2 W10 1 R/W These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Section 6 Bus Controller 6.3.4 Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. This register should be set initial value and not be modified in the H8S/2212 Group. Bit Bit Name Initial Value R/W Description 7 ICIS1 1 Idle Cycle Insert 1: R/W Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Section 6 Bus Controller 6.3.5 Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. The functions selected by this register are available only in the H8S/2218 Group. This register should not be modified in the H8S/2212 Group. Bit Bit Name Initial Value R/W Description 7 BRLE* 0 Bus Release Enable R/W Enables or disables external bus release. 0: External bus release is disabled.
Section 6 Bus Controller 6.3.6 Pin Function Control Register (PFCR) PFCR performs address output control in external extended mode. When using the USB with the emulator (E6000), enable the A8 and A9 output by setting AE3 to AE0 to 0010. Bit Bit Name Initial Value R/W 7 to ⎯ Undefined R/W 4 Description Reserved The write value should always be 0.
Section 6 Bus Controller 6.4 Bus Control 6.4.1 Area Divisions In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS5) can be output for areas 0 to 5. Note: * Not available in this LSI.
Section 6 Bus Controller 6.4.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for memory and internal I/O registers except for the onchip USB and RTC are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 6 Bus Controller Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn 0 ASTn 0 1 Wn1 ⎯ 0 1 1 0 1 ⎯ 0 1 6.4.3 Wn0 ⎯ 0 1 0 1 ⎯ 0 1 0 1 Bus Specifications (Basic Bus Interface) Number of Number of Bus Width Access States Program Wait States 16 2 0 3 0 1 2 3 8 2 0 3 0 1 2 3 Bus Interface for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode.
Section 6 Bus Controller the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. 6.4.4 Chip Select Signals In the H8S/2218 Group chip select signals (CS0 to CS5) can be output to areas 0 to 5, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 5) output timing.
Section 6 Bus Controller 6.5 Basic Timing The CPU is driven by a system clock (φ), denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip peripheral modules, and the external address space. 6.5.1 On-Chip Memory (ROM, RAM) Access Timing On-chip memory is accessed in one state.
Section 6 Bus Controller Bus cycle T1 φ Address bus* Unchanged AS* High RD* High HWR, LWR* High Data bus* High-impedance state Note: * Supported only by the H8S/2218 Group. Figure 6.5 Pin States during On-Chip Memory Access 6.5.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states except on-chip USB and RTC. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus* Unchanged AS* High RD* High HWR, LWR* High Data bus* High-impedance state Note: * Supported only by the H8S/2218 Group. Figure 6.7 Pin States during On-Chip Peripheral Module Access 6.5.3 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6.6.
Section 6 Bus Controller 6.6 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.6.1 Data Size and Data Alignment (Supported Only by the H8S/2218 Group) Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller Upper data bus Lower data bus D15 D8 D7 D0 Byte size · Even address Byte size · Odd address Word size 1st bus cycle Longword size 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.6.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces in the H8S/2218 Group. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus.
Section 6 Bus Controller 6.6.3 Basic Timing 8-Bit 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit 2-state access space in the H8S/2218 Group. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
Section 6 Bus Controller 8-Bit 3-State Access Space (Except Area 6): Figure 6.11 shows the bus timing for an 8-bit 3state access space in the H8S/2218 Group. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Section 6 Bus Controller 8-Bit 3-State Access Space (Area 6 and RTC): Figure 6.12 shows the bus timing for area 6 and RTC area (address = H'FFFF40 to H'FFFF5F). When the areas are accessed, the data bus cannot be used. Wait states cannot be inserted.
Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit 2-state access space in the H8S/2218 Group. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 5 Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.7.00 Dec.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 5 Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.7.00 Dec.
Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit 3-state access space in the H8S/2218 Group. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 5 Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.7.00 Dec.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 5 Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.7.00 Dec.
Section 6 Bus Controller 6.6.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
Section 6 Bus Controller Figure 6.19 shows an example of wait state insertion timing. In the H8S/2212 Group, the WAITE bit in BCRH should not be set to 1. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: ↓ indicates the timing of WAIT pin sampling. Figure 6.19 Example of Wait State Insertion Timing Rev.7.00 Dec.
Section 6 Bus Controller 6.7 Burst ROM Interface With the H8S/2218 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only.
Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 φ Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) Rev.7.00 Dec.
Section 6 Bus Controller 6.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.6.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.
Section 6 Bus Controller Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T1 T2 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD Data bus Data bus Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) T2 T3 TI T1 Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6.22 Example of Idle Cycle Operation (1) Rev.7.00 Dec.
Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.23 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data.
Section 6 Bus Controller Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD T2 T3 Bus cycle B TI T1 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6.24 Relationship between Chip Select (CS) and Read (RD) Table 6.4 shows pin states in an idle cycle. Table 6.
Section 6 Bus Controller 6.9 Bus Release The H8S/2218 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. In external extended mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI.
Section 6 Bus Controller Figure 6.25 shows the timing for transition to the bus-released state. CPU cycle T0 T1 CPU cycle External bus released state T2 φ High impedance Address bus Address High impedance Data bus High impedance CSn High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [1] [2] [3] [4] [5] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state.
Section 6 Bus Controller 6.10 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 6 Bus Controller • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. • If the CPU is in sleep mode, it transfers the bus immediately. DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated.
Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1 Features The features of the DMAC are listed below.
Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1.
Section 7 DMA Controller (DMAC) 7.2 Register Configuration The DMAC registers are listed below.
Section 7 DMA Controller (DMAC) Table 7.
Section 7 DMA Controller (DMAC) 7.3 7.3.1 Register Descriptions Memory Address Registers (MAR) • Short Address Mode MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR.
Section 7 DMA Controller (DMAC) 7.3.3 Execute Transfer Count Register (ETCR) • Short Address Mode ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. ETCR is not initialized by a reset or in standby mode.
Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Register (DMACR) DMACR controls the operation of each DMAC channel. • Short Address Mode (common to DMACRA and DMACRB) Bit Bit Name Initial Value R/W 7 DTSZ 0 R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 6 DTID 0 R/W Data Transfer Increment/Decrement Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 Repeat Enable RPE 0 R/W Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 2 DTF2 0 R/W These bits select the data transfer factor (activation source).
Section 7 DMA Controller (DMAC) • Full Address Mode (DMACRA) Bit Bit Name Initial Value R/W 15 DTSZ 0 R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 14 SAID 0 R/W Source Address Increment/Decrement 13 SAIDE 0 R/W Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 ⎯ to 8 Reserved All 0 R/W Although these bits are readable/writable, only 0 should be written to. • Full Address Mode (DMACRB) Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W Description Reserved Although this bit is readable/writable, only 0 should be written to.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 R/W R/W R/W R/W Description Data Transfer Factor These bits select the data transfer factor (activation source).
Section 7 DMA Controller (DMAC) 7.3.5 DMA Band Control Register (DMABCR) DMABCR controls the operation of each DMAC channel. • Short Address Mode Bit Bit Name Initial Value R/W Description 15 FAE1 Full Address Enable 1 0 R/W Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W 11 10 9 8 DTA1B DTA1A DTA0B DTA0A 0 0 0 0 R/W R/W R/W R/W Description Data Transfer Acknowledge These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU.
Section 7 DMA Controller (DMAC) • Full Address Mode Bit Bit Name Initial Value R/W Description 15 FAE1 0 Full Address Enable 1 R/W Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Acknowledge Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 8 Reserved – 0 R/W Although this bit is readable/writable, only 0 should be written to. Data Transfer Master Enable Together with the DTE bit, this bit controls enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Enable When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Interrupt Enable B Enables or disables an interrupt to the CPU when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU.
Section 7 DMA Controller (DMAC) 7.4 Operation 7.4.1 Transfer Modes Table 7.2 lists the DMAC modes. Table 7.
Section 7 DMA Controller (DMAC) 7.4.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.3 summarizes register functions in sequential mode. Table 7.
Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Notes: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.2 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
Section 7 DMA Controller (DMAC) Sequential mode setting Set DMABCRH [1] Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] [1] Set each bit in DMABCRH. · Clear the FAE bit to 0 to select short address mode. · Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
Section 7 DMA Controller (DMAC) 7.4.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.4 summarizes register functions in idle mode. Table 7.
Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. Figure 7.5 shows an example of the setting procedure for idle mode.
Section 7 DMA Controller (DMAC) 7.4.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
Section 7 DMA Controller (DMAC) In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below.
Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. Figure 7.7 shows an example of the setting procedure for repeat mode.
Section 7 DMA Controller (DMAC) 7.4.5 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.
Section 7 DMA Controller (DMAC) Figure 7.8 illustrates operation in normal mode. Address TA Transfer Address TB Address BB Address BA Notes: Address TA = LA Address TB = LB Address BA = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) Address BB = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) LA = Value set in MARA LB = Value set in MARB N = Value set in ETCRA Figure 7.8 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
Section 7 DMA Controller (DMAC) Figure 7.9 shows an example of the setting procedure for normal mode. Normal mode setting Set DMABCRH [1] Set transfer source and transfer destination [2] addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Normal mode [1] Set each bit in DMABCRH. · Set the FAE bit to 1 to select full address mode. · Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Section 7 DMA Controller (DMAC) 7.4.6 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB.
Section 7 DMA Controller (DMAC) Figure 7.10 illustrates operation in block transfer mode when MARB is designated as a block area.
Section 7 DMA Controller (DMAC) Figure 7.11 illustrates operation in block transfer mode when MARA is designated as a block area.
Section 7 DMA Controller (DMAC) Start (DTE = DTME = 1) Transfer request? No Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ ETCRAL = ETCRAL–1 ETCRAL = H'00 No Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure
Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.13 shows an example of the setting procedure for block transfer mode.
Section 7 DMA Controller (DMAC) 7.4.7 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode, as shown in table 7.8. Table 7.
Section 7 DMA Controller (DMAC) Activation by USB Request: The USB request (DREQ signal) is specified as a DMAC activation source. The USB request is generated by the level sense. In full-address normal mode, the USB request is carried out as follows. While the DREQ signal is kept high, the DMAC waits for the transfer request. While the DREQ signal is kept low, the DMAC releases the bus each time a byte is transferred and the transfer is performed continuously.
Section 7 DMA Controller (DMAC) 7.4.8 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.14. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
Section 7 DMA Controller (DMAC) 7.4.9 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.15 shows a transfer example in which TEND* output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode): Figure 7.16 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
Section 7 DMA Controller (DMAC) Full Address Mode (Burst Mode): Figure 7.17 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA DMA read DMA write DMA read DMA write DMA read DMA write dead φ Address bus RD HWR LWR TEND* Last transfer cycle Bus release Bus release Burst transfer Note: * This LSI does not support TEND output. Figure 7.
Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode): Figure 7.18 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Section 7 DMA Controller (DMAC) DREQ Signal Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ signal is selected to 1. Figure 7.19 shows an example of DREQ level activated normal mode transfer.
Section 7 DMA Controller (DMAC) 7.4.10 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9 summarizes the priority order for DMAC channels. Table 7.
Section 7 DMA Controller (DMAC) 7.4.11 Relation between the DMAC and External Bus Requests There can be no break between a DMA cycle read and a DMA cycle write. This means that an external bus release cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, an external bus released state may be inserted after a write cycle.
Section 7 DMA Controller (DMAC) Resumption of transfer on interrupted channel DTE = 1 DTME = 0 [1] Check that DTE = 1 and DTME = 0 in DMABCRL [2] Write 1 to the DTME bit. [1] No Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.21 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt 7.4.
Section 7 DMA Controller (DMAC) 7.4.14 Clearing Full Address Mode Figure 7.23 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure.
Section 7 DMA Controller (DMAC) 7.5 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.10 shows the interrupt sources and their priority order. Table 7.
Section 7 DMA Controller (DMAC) 7.6 Usage Notes 7.6.1 DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. 1.
Section 7 DMA Controller (DMAC) 2. If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.26. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control Idle DMA register operation Note: [1] Transfer source Transfer destination Read Write Idle [2] The lower word of MAR is the updated value after the operation in [1]. Figure 7.
Section 7 DMA Controller (DMAC) 7.6.4 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ signal falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer.
Section 7 DMA Controller (DMAC) Rev.7.00 Dec.
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 and table 8.2 summarize the port functions of the H8S/2218 Group and H8S/2212 Group respectively. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have DR and DDR.
Section 8 I/O Ports Port Description Port 9 P97/AN15 General input port also P96/AN14 functioning as A/D converter analog input pins Port A General I/O port also functioning as SCI_2 I/O pins and address bus output pins PA3/A19/SCK2 PA3/SCK2 PA2/A18/RxD2 PA2/RxD2 PA1/A17/TxD2 PA1/TxD2 PA0/A16 PA0 General I/O port also functioning as address bus output pins PB7/A15 PB7 PB6/A14 PB6 PB5/A13 PB5 PB4/A12 PB4 PB3/A11 PB3 PB2/A10 PB2 PB1/A9 PB1 Port B Modes 4 and 5 Mode 6 PB0/A8 Po
Section 8 I/O Ports Port Description Modes 4 and 5 Port E General I/O port 8-bit bus mode: PE7 also functioning as 16-bit bus mode: D7 data bus I/O pins 8-bit bus mode: PE6 Mode 6 Mode 7 PE7 Input/Output Type On-chip input pull-up MOS PE6 16-bit bus mode: D6 8-bit bus mode: PE5 PE5 16-bit bus mode: D5 8-bit bus mode: PE4 PE4 16-bit bus mode: D4 8-bit bus mode: PE3 PE3 16-bit bus mode: D3 8-bit bus mode: PE2 PE2 16-bit bus mode: D2 8-bit bus mode: PE1 PE1 16-bit bus mode: D1 8-bit bus mod
Section 8 I/O Ports Port Description Modes 4 and 5 Mode 6 Mode 7 Port G General I/O port also functioning as bus control output pins and interrupt Input pins When DDR = 0 (after reset in mode 6): PG4 When DDR = 1 (after reset in modes 4, 5): CS0 PG4 When DDR = 0: PG3 PG3 Input/Output Type Schmitt trigger input (IRQ7) When DDR = 1: CS1 When DDR = 0: PG2 PG2 When DDR = 1: CS2 When DDR = 0: PG1/IRQ7 PG1/IRQ7 When DDR = 1: CS3/IRQ7 Table 8.
Section 8 I/O Ports Mode 7 Input/Output Type Port Description Port A General I/O port PA3/SCK2 also functioning PA2/RxD2 as SCI_2 I/O pins PA1/TxD2 On-chip input pull-up MOS Open-drain output Port E General I/O port On-chip input pull-up MOS PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Port F Port G General I/O port also functioning as interrupt input pins General I/O port also functioning as interrupt input pins When DDR = 0 (after reset): PF7 When DDR = 1: φ PF3/ADTRG/IRQ3 Schmitt trigger input (IRQ3,
Section 8 I/O Ports 8.1 Port 1 In the H8S/2218 Group, the port 1 is an 8-bit I/O port also functioning as address bus pins, TPU I/O pins, and external interrupt input pins. In the H8S/2212 Group, the port 1 is an 8-bit I/O port also functioning as TPU I/O pins and external interrupt input pins. The port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 8.1.
Section 8 I/O Ports 8.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Store output data for a pin that functions as a general output port. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 8.1.3 Port 1 Register (PORT1) PORT1 indicates the pin states of the port 1.
Section 8 I/O Ports 8.1.4 Pin Functions Pin Functions of H8S/2218 Group Port 1 pins also function as address bus (A23 to A20) output pins, TPU I/O pins, and external interrupt input (IRQ0 and IRQ1) pins. The correspondence between the register specification and the pin functions is shown below. Table 8.
Section 8 I/O Ports Table 8.6 P14 Pin Function TPU Channel 1 Setting*1 Output Setting ⎯ 0 1 TIOCA1 output pin P14 input pin P14 output pin P14DDR Pin Function Input Setting or Initial Value TIOCA1 input pin IRQ0 input pin* 2 Notes: 1. For details on the TPU channel setting, refer to section 9, 16-Bit Timer Pulse Unit (TPU). 2. When this pin is used as an external interrupt pin, this pin must not be used for another function. Table 8.
Section 8 I/O Ports Table 8.9 P11 Pin Function AE3 to AE0*2 TPU Channel 0 Setting*1 Other than B'1110 to B'1111 Output Setting ⎯ Input Setting or Initial Value ⎯ 0 1 ⎯ TIOCB0 output pin P11 input pin P11 output pin A21 output pin*2 P11DDR Pin Function B'1110 to B'1111 TIOCB0 input pin Notes: 1. For details on the TPU channel setting, refer to section 9, 16-Bit Timer Pulse Unit (TPU). 2. Valid in modes 4, 5, and 6. Table 8.
Section 8 I/O Ports Table 8.12 P16 Pin Function TPU Channel 2 Setting*1 Output Setting ⎯ 0 1 TIOCA2 output pin P16 input pin P16 output pin P16DDR Pin Function Input Setting or Initial Value TIOCA2 input pin IRQ1 input pin* 2 Notes: 1. For details on the TPU channel setting, refer to section 9, 16-Bit Timer Pulse Unit (TPU). 2. When this pin is used as an external interrupt pin, this pin must not be used for another function. Table 8.
Section 8 I/O Ports Table 8.15 P13 Pin Function TPU Channel 0 Setting* Output Setting ⎯ 0 1 TIOCD0 output pin P13 input pin P13 output pin P13DDR Pin Function Input Setting or Initial Value TIOCD0 input pin TCLKB input pin Note: * For details on the TPU channel setting, refer to section 9, 16-Bit Timer Pulse Unit (TPU). Table 8.
Section 8 I/O Ports 8.2 Port 3 The port 3 is a 4-bit I/O port also functioning as the SCI I/O pins and external interrupt input (IRQ4) pins. The port 3 of the H8S/2218 Group has the same function as that of the H8S/2212 Group. The port 3 has the following registers. • • • • Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open-drain control register (P3ODR) 8.2.
Section 8 I/O Ports 8.2.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W 7 ⎯ ⎯ Undefined Description Reserved This bit is undefined and cannot be modified. 6 P36DR 5 to ⎯ 3 0 R/W Undefined ⎯ Reserved These bits are undefined and cannot be modified. 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 8.2.3 Stores output data for a pin that functions as a general output port.
Section 8 I/O Ports 8.2.4 Port 3 Open-Drain Control Register (P3ODR) P3ODR controls the PMOS on/off state for each port 3 pin. Bit Bit Name Initial Value R/W 7 ⎯ ⎯ Undefined Description Reserved This bit is undefined and cannot be modified. 6 P36ODR 5 to ⎯ 3 0 R/W Undefined ⎯ Reserved These bits are undefined and cannot be modified. 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W 8.2.
Section 8 I/O Ports Table 8.20 P32 Pin Function CKE1 in SCR_0 0 C/A in SMR_0 Pin Function 1 ⎯ 1 ⎯ ⎯ 0 CKE0 in SCR_0 P32DDR 1 0 0 1 ⎯ ⎯ ⎯ P32 input pin P32 output pin SCK0 output pin SCK0 output pin SCK0 input pin IRQ4 input pin* Note: * When this pin is used as an external interrupt pin, this pin must not be used for another function. Table 8.21 P31 Pin Function RE in SCR_0 0 Pin Function 1 0 1 ⎯ P31 input pin P31 output pin RxD0 input pin P31DDR Table 8.
Section 8 I/O Ports 8.3 Port 4 The port 4 is a 4-bit input port also functioning as A/D converter analog input pins. The port 4 of the H8S/2218 Group has the same function as that of the H8S/2212 Group. The port 4 has the following register. • Port 4 register (PORT4) 8.3.1 Port 4 Register (PORT4) PORT4 indicates the pin states of the port 4. Bit Bit Name Initial Value 7 to ⎯ 4 Undefined R/W ⎯ Description Reserved These bits are undefined.
Section 8 I/O Ports 8.4 Port 7 In the H8S/2218 Group, the port 7 is a 3-bit I/O port also functioning as bus control output pins and manual reset input pins. In the H8S/2212 Group, the port 7 is a 3-bit I/O port also functioning as H-UDI pins. The port 7 has the following registers. • Port 7 data direction register (P7DDR) • Port 7 data register (P7DR) • Port 7 register (PORT7) 8.4.1 Port 7 Data Direction Register (P7DDR) P7DDR specifies input or output for the pins of the port 7.
Section 8 I/O Ports Bit Bit Name Initial Value R/W Description 1 P71DDR 0 W (H8S/2218 Group) 0 P70DDR 0 W Setting a P7DDR bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. (H8S/2212 Group) Reserved These bits are undefined and cannot be modified. 8.4.2 Port 7 Data Register (P7DR) P7DR stores output data for the port 7 pins.
Section 8 I/O Ports 8.4.3 Port 7 Register (PORT7) PORT7 indicates the pin states of the port 7. Bit Bit Name Initial Value R/W Description 7 P77 ⎯* ⎯ (H8S/2218 Group) 6 P76 ⎯* ⎯ 5 P75 ⎯* ⎯ Reserved These bits are undefined and cannot be modified. (H8S/2212 Group) If P7DDR bits are set to 1, the P7DR value is read. If P7DDR bits are cleared to 0, the pin states are read. 4 P74 ⎯* R (H8S/2218 Group) If the port 7 is read while P7DDR bits are set to 1, the P7DR value is read.
Section 8 I/O Ports 8.4.4 Pin Functions Pin Functions of H8S/2218 Group Port 7 pins also function as bus control output pins and manual reset input pins. The correspondence between the register specification and the pin functions is shown below. Table 8.23 P74 Pin Function MRESE 0 0 1 ⎯ P74 input pin P74 output pin MRES input pin P74DDR Pin Function 1 Table 8.
Section 8 I/O Ports Table 8.27 P76 Pin Function EMLE 0 0 1 ⎯ P76 input pin P76 output pin TCK input pin P76DDR Pin Function 1 Table 8.28 P75 Pin Function EMLE 0 0 1 ⎯ P75 input pin P75 output pin TMS input pin P75DDR Pin Function 8.5 1 Port 9 The port 9 is a 2-bit input port also functioning as A/D converter analog input pins. The port 9 of the H8S/2218 Group has the same function as that of the H8S/2212 Group. • Port 9 register (PORT9) 8.5.
Section 8 I/O Ports 8.6 Port A In the H8S/2218 Group, the port A is a 4-bit I/O port also functioning as address bus (A19 to A16) output pins and SCI I/O pins. In the H8S/2212 Group, the port A is a 3-bit I/O port also functioning as SCI I/O pins. The port A has the following registers. • • • • • Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A pull-up MOS control register (PAPCR) Port A open-drain control register (PAODR) 8.6.
Section 8 I/O Ports 8.6.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value 7 to ⎯ 4 R/W Description Undefined ⎯ Reserved These bits are undefined and cannot be modified. 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR* 0 R/W Store output data for a pin that functions as a general output port. Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit cannot be modified. 8.6.
Section 8 I/O Ports 8.6.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls the on/off state of the port A input pull-up MOS. PAPCR is valid for port input and SCI input pins. Bit Bit Name Initial Value 7 to ⎯ 4 R/W Description Undefined ⎯ Reserved These bits are undefined and cannot be modified. 3 PA3PCR 0 R/W 2 PA2PCR 0 R/W 1 PA1PCR 0 R/W 0 PA0PCR* 0 R/W When a pin functions as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
Section 8 I/O Ports 8.6.6 Pin Functions Pin Functions of H8S/2218 Group Port A pins also function as address bus (A19 to A16) output pins and SCI_2 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 8.
Section 8 I/O Ports Table 8.31 PA1 Pin Function Operating mode AE3 to AE0 Modes 4 to 6 B'101× or B'11×× TE in SCR_2 — PA1DDR — Pin Function Mode 7 Other than B'101× or B'11×× 0 0 — 1 1 — 0 1 0 1 — A17 PA1 PA1 TxD2 PA1 PA1 TxD2 output pin input pin output pin output pin input pin output pin output pin Table 8.
Section 8 I/O Ports Table 8.34 PA2 Pin Function RE in SCR_2 PA2DDR Pin Function 0 1 0 1 ⎯ PA2 input pin PA2 output pin RxD2 input pin Table 8.35 PA1 Pin Function TE in SCR_2 PA1DDR Pin Function 8.6.7 0 1 0 1 ⎯ PA1 input pin PA1 output pin TxD2 output pin Port A Input Pull-Up MOS States The port A has an on-chip input pull-up MOS function that can be controlled by software. The input pull-up MOS can be specified as the on or off state for individual bits. Table 8.
Section 8 I/O Ports 8.7 Port B (H8S/2218 Group Only) The port B is an 8-bit I/O port also functioning as address bus (A15 to A8) output pins. The port B has the following registers. Note: When the USB is used while the E6000 emulator is used, the AE3 to AE0 bits in PFCR must be set so that the PB1 and PB0 pins output addresses A9 and A8. This note applies to both the H8S/2218 Group and H8S/2212 Group.
Section 8 I/O Ports 8.7.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W Store output data for a pin that functions as a general output port. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 8.7.3 Port B Register (PORTB) PORTB indicates the pin states of the port B.
Section 8 I/O Ports 8.7.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls the on/off state of the port B input pull-up MOS. PBPCR is valid for port input pins. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W 5 PB5PCR 0 R/W When a pin functions as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 4 PB4PCR 0 R/W 3 PB3PCR 0 R/W 2 PB2PCR 0 R/W 1 PB1PCR 0 R/W 0 PB0PCR 0 R/W Rev.7.00 Dec.
Section 8 I/O Ports 8.7.5 Pin Functions Port B pins also function as address bus (A15 to A9) output pins. The correspondence between the register specification and the pin functions is shown below. Note: When using the USB with the emulator (E6000), set A9 and A8 as address bus output pins. Table 8.
Section 8 I/O Ports Table 8.40 PB4 Pin Function Operating mode AE3 to AE0 PB4DDR Pin Function Modes 4 to 6 Other than B'0100 or B'00×× — Mode 7 B'0100 or B'00×× 0 A12 output pin 1 PB4 PB4 input pin output pin — 0 1 PB4 input pin PB4 output pin Table 8.41 PB3 Pin Function Operating mode AE3 to AE0 PB3DDR Pin Function Modes 4 to 6 Other than B'00×× Mode 7 B'00×× — — 0 1 0 1 A11 output pin PB3 input pin PB3 output pin PB3 input pin PB3 output pin Table 8.
Section 8 I/O Ports Table 8.44 PB0 Pin Function Operating mode AE3 to AE0 Modes 4 to 6 Other than B'0000 PB0DDR Pin Function Mode 7 B'0000 — — 0 1 0 1 A8 output pin PB0 input pin PB0 output pin PB0 input pin PB0 output pin Legend: ×: Don't care. 8.7.6 Port B Input Pull-Up MOS States The port B has an on-chip input pull-up MOS function that can be controlled by software. The input pull-up MOS can be specified as the on or off state for individual bits. Table 8.
Section 8 I/O Ports 8.8 Port C (H8S/2218 Group Only) The port C is an 8-bit I/O port also functioning as address bus (A7 to A0) output pins. The port C has the following registers. Note: When the RTC and USB are used while the E6000 emulator is used, the PC7DDR to PC0DDR bits in PCDDR must be set so that the PC7 to PC0 pins output addresses A7 to A0. This note applies to both the H8S/2218 Group and H8S/2212 Group.
Section 8 I/O Ports 8.8.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Store output data for a pin that functions as a general output port. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 8.8.3 Port C Register (PORTC) PORTC indicates the pin states of the port C.
Section 8 I/O Ports 8.8.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls the on/off state of the port C input pull-up MOS. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W 5 PC5PCR 0 R/W When a pin functions as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 4 PC4PCR 0 R/W 3 PC3PCR 0 R/W 2 PC2PCR 0 R/W 1 PC1PCR 0 R/W 0 PC0PCR 0 R/W 8.8.
Section 8 I/O Ports Table 8.48 PC5 Pin Function Operating Mode PC5DDR Pin Function Modes 4 and 5 Mode 6 Mode 7 ⎯ 0 1 0 1 A5 output pin PC5 input pin A5 output pin PC5 input pin PC5 output pin Table 8.49 PC4 Pin Function Operating Mode PC4DDR Pin Function Modes 4 and 5 Mode 6 Mode 7 ⎯ 0 1 0 1 A4 output pin PC4 input pin A4 output pin PC4 input pin PC4 output pin Table 8.
Section 8 I/O Ports Table 8.53 PC0 Pin Function Operating Mode Modes 4 and 5 8.8.6 Mode 7 ⎯ 0 1 0 1 A0 output pin PC0 input pin A0 output pin PC0 input pin PC0 output pin PC0DDR Pin Function Mode 6 Port C Input Pull-Up MOS States The port C has an on-chip input pull-up MOS function that can be controlled by software. The input pull-up MOS can be used in modes 6 and 7, and can be specified as the on or off state for individual bits. Table 8.54 summarizes the input pull-up MOS states.
Section 8 I/O Ports 8.9 Port D (H8S/2218 Group Only) The port D is an 8-bit I/O port also functioning as data bus (D15 to D8) I/O pins. The port D has the following registers. • • • • Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) 8.9.1 Port D Data Direction Register (PDDDR) PDDDR specifies input or output for the pins of the port D.
Section 8 I/O Ports 8.9.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Store output data for a pin that functions as a general output port. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 8.9.3 Port D Register (PORTD) PORTD indicates the pin states of the port D.
Section 8 I/O Ports 8.9.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls the on/off state of the port D input pull-up MOS. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W 5 PD5PCR 0 R/W When a pin functions as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 8.9.
Section 8 I/O Ports Table 8.58 PD4 Pin Function Operating Mode Modes 4 to 6 ⎯ 0 1 D12 input/output pin PD4 input pin PD4 output pin PD4DDR Pin Function Mode 7 Table 8.59 PD3 Pin Function Operating Mode Modes 4 to 6 ⎯ 0 1 D11 input/output pin PD3 input pin PD3 output pin PD3DDR Pin Function Mode 7 Table 8.60 PD2 Pin Function Operating Mode Modes 4 to 6 ⎯ 0 1 D10 input/output pin PD2 input pin PD2 output pin PD2DDR Pin Function Mode 7 Table 8.
Section 8 I/O Ports 8.9.6 Port D Input Pull-Up MOS States The port D has an on-chip input pull-up MOS function that can be controlled by software. The input pull-up MOS can be used in mode 7, and can be specified as the on or off state for individual bits. Table 8.63 summarizes the input pull-up MOS states. Table 8.
Section 8 I/O Ports 8.10 Port E The port E is an 8-bit I/O port also functioning as data bus (D7 to D0) I/O pins. The port E has the following registers. • • • • Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) 8.10.1 Port E Data Direction Register (PEDDR) PEDDR specifies input or output for the pins of the port E.
Section 8 I/O Ports 8.10.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Store output data for a pin that functions as a general output port. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 8.10.3 Port E Register (PORTE) PORTE indicates the pin states of the port E.
Section 8 I/O Ports 8.10.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls the on/off state of the port E input pull-up MOS. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W 5 PE5PCR 0 R/W When a pin functions as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W 8.10.
Section 8 I/O Ports Table 8.66 PE5 Pin Function Operating Mode Modes 4 to 6 Mode 7 ⎯ Bus Mode 8-bit bus mode PE5DDR 0 1 ⎯ 0 1 PE5 input pin PE5 output pin D5 input/output pin PE5 input pin PE5 output pin Pin Function 16-bit bus mode Table 8.67 PE4 Pin Function Operating Mode Modes 4 to 6 Bus Mode 8-bit bus mode ⎯ 16-bit bus mode 0 1 ⎯ 0 1 PE4 input pin PE4 output pin D4 input/output pin PE4 input pin PE4 output pin PE4DDR Pin Function Mode 7 Table 8.
Section 8 I/O Ports Table 8.70 PE1 Pin Function Operating Mode Modes 4 to 6 Mode 7 ⎯ Bus Mode 8-bit bus mode PE1DDR 0 1 ⎯ 0 1 PE1 input pin PE1 output pin D1 input/output pin PE1 input pin PE1 output pin Pin Function 16-bit bus mode Table 8.
Section 8 I/O Ports Table 8.75 PE4 Pin Function PE4DDR Pin Function 0 1 PE4 input pin PE4 output pin 0 1 PE3 input pin PE3 output pin 0 1 PE2 input pin PE2 output pin 0 1 PE1 input pin PE1 output pin 0 1 PE0 input pin PE0 output pin Table 8.76 PE3 Pin Function PE3DDR Pin Function Table 8.77 PE2 Pin Function PE2DDR Pin Function Table 8.78 PE1 Pin Function PE1DDR Pin Function Table 8.79 PE0 Pin Function PE0DDR Pin Function 8.10.
Section 8 I/O Ports Table 8.80 Input Pull-Up MOS States (Port E) Power-On Reset Pins Data input/output (16-bit bus mode in modes 4 to 6), port output (8-bit bus mode in modes 4 to 6, mode 7) Hardware Standby Mode Off Port input (8-bit bus mode in modes 4 to 6, mode 7) Manual Reset Software Standby Mode In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off. 8.
Section 8 I/O Ports 8.11.1 Port F Data Direction Register (PFDDR) PFDDR specifies input or output for the pins of the port F. Since PFDDR is a write-only register, the bit manipulation instructions must not be used to write PFDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Section 8 I/O Ports 8.11.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR* 0 R/W Store output data for a pin that functions as a general output port. 5 PF5DR* 0 R/W 4 PF4DR* 0 R/W 3 PF3DR 0 R/W 2 PF2DR* 0 R/W 1 PF1DR* 0 R/W 0 PF0DR 0 R/W Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit cannot be modified. 8.11.
Section 8 I/O Ports 8.11.4 Clock Output Control Register (OUTCR) OUTCR specifies the clock frequency output from the PF7 pin. Bit Bit Name 7 to ⎯ 3 Initial Value R/W Undefined ⎯ Description Reserved The write value should always be 0.
Section 8 I/O Ports Table 8.83 PF5 Pin Function Operating Mode Modes 4 to 6 ⎯ 0 1 RD output pin PF5 input pin PF5 output pin PF5DDR Pin Function Mode 7 Table 8.84 PF4 Pin Function Operating Mode Modes 4 to 6 ⎯ 0 1 HWR output pin PF4 input pin PF4 output pin PF4DDR Pin Function Mode 7 Table 8.
Section 8 I/O Ports Table 8.87 PF1 Pin Function Operating Mode Modes 4 to 6 BRLE 0 ⎯ 1 0 1 ⎯ 0 1 PF1 input pin PF1 output pin BACK output pin PF1 input pin PF1 output pin PF1DDR Pin Function Mode 7 Table 8.
Section 8 I/O Ports Table 8.90 PF3 Pin Function PF3DDR 0 Pin Function 1 PF3 input pin PF3 output pin ADTRG input pin* 1 IRQ3 input pin*2 Notes: 1. ADTRG input pin when TRGS0 = TRGS1 = 1. 2. When this pin is used as an external interrupt input pin, this pin must not be used as an I/O pin for another function. Table 8.
Section 8 I/O Ports 8.12.1 Port G Data Direction Register (PGDDR) PGDDR specifies input or output for the pins of the port G. Since PGDDR is a write-only register, the bit manipulation instructions must not be used to write PGDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits. Bit Bit Name 7 to ⎯ 5 Initial Value R/W Description Undefined ⎯ Reserved These bits are undefined and cannot be modified.
Section 8 I/O Ports 8.12.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value 7 to ⎯ 5 4 Undefined R/W ⎯ Description Reserved These bits are undefined and cannot be modified. PG4DR*1 0 1 R/W 3 PG3DR* 0 R/W 2 PG2DR*1 0 R/W 1 PG1DR 0 R/W 0 PG0DR*2 0 R/W Store output data for a pin that functions as a general output port. Notes: 1. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.
Section 8 I/O Ports 8.12.4 Pin Functions Pin Functions of H8S/2218 Group Port G pins also function as external interrupt input (IRQ7) pins and bus control signal output (CS0 to CS3) pins. The correspondence between the register specification and the pin functions is shown below. Table 8.92 PG4 Pin Function Operating Mode Modes 4 to 6 PG4DDR Pin Function Mode 7 0 1 0 1 PG4 input pin CS0 output pin PG4 input pin PG4 output pin Table 8.
Section 8 I/O Ports Pin Functions of H8S/2212 Group Port G pins also function as external interrupt input (IRQ7) pins and H-UDI (TDI) pins. The correspondence between the register specification and the pin functions is shown below. Table 8.96 PG1 Pin Function PG1DDR Pin Function 0 1 PG1 input pin PG1 output pin IRQ7 input pin* Note: * When this pin is used as an external interrupt input pin, this pin must not be used as an I/O pin for another function. Table 8.
Section 8 I/O Ports Table 8.98 Examples of Ways to Handle Unused Input Pins Port Name Pin Handling Example Port 1 Connect each pin to Vcc (pull-up) or to Vss (pull-down) via a resistor. Port 3 Port 4 Connect each pin to AVcc (pull-up) or to AVss (pull-down) via a resistor. Port 7 Connect each pin to Vcc (pull-up) or to Vss (pull-down) via a resistor. Port 9 Connect each pin to AVcc (pull-up) or to AVss (pull-down) via a resistor.
Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 9.1 and figure 9.1, respectively. 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Legend: TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR(H, L): TIER: TSR: TGR(A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register TImer general registers (A, B, C, D) Figure 9.1 Block Diagram of TPU Rev.7.00 Dec.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources • Compare match or input capture 0A • Compare match or input capture 1A • Compare match or input captu
Section 9 16-Bit Timer Pulse Unit (TPU) 9.2 Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3 Register Descriptions The TPU has the following registers.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNTcounter clearing source. See tables 9.3 and 9.4 for details.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.5 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 4 BFA R/W Buffer Operation A 0 Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE R/W A/D Conversion Start Request Enable 0 Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 1 TGIEB R/W TGR Interrupt Enable B 0 Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 4 TCFV R/(W)* Overflow Flag 0 Description Status flag that indicates that TCNT overflow has occurred. The write value should always be 0 to clear this flag.
Section 9 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 1 TGFB R/(W)* Input Capture/Output Compare Flag B 0 Description Status flag that indicates the occurrence of TGRB input capture or compare match. The write value should always be 0 to clear this flag.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 9.3.7 Timer General Register (TGR) The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value 7 to – 3 All 0 R/W Description – Reserved The write value should always be 0.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4 9.4.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 9.2. Internal data bus H Bus master L Module data bus Bus interface TCNTH TCNTL Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master L Module data bus Bus interface TCR Figure 9.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 9.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 9.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] Rev.7.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.5 Operation 9.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Section 9 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 9 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 9.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 9.9 shows an example of the setting procedure for waveform output by compare match.
Section 9 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 9.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB No change 0 output Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. 1. Example of input capture operation setting procedure Figure 9.12 shows an example of the input capture operation setting procedure.
Section 9 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 9.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation.
Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 9.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.5.3 Buffer Operation Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9.17 shows the register combinations used in buffer operation. Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 9.18 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] Set buffer operation [2] Start count [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation 1. When TGR is an output compare register Figure 9.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 9 16-Bit Timer Pulse Unit (TPU) 2. When TGR is an input capture register Figure 9.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently.
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.18 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 0 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TGRD_0 1 TIOCD0 TGRA_1 TIOCA1 TGRB_1 2 TIOCC0 TIOCA1 TIOCB1 TGRA_2 TIOCA2 TGRB_2 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Example of PWM Mode Setting Procedure: Figure 9.21 shows an example of the PWM mode setting procedure.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation: Figure 9.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 9.26 shows an example of phase counting mode 1 operation, and table 9.20 summarizes the TCNT up/down-count conditions.
Section 9 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 9.27 shows an example of phase counting mode 2 operation, and table 9.21 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.27 Example of Phase Counting Mode 2 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 9.28 shows an example of phase counting mode 3 operation, and table 9.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 9.28 Example of Phase Counting Mode 3 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 9.29 shows an example of phase counting mode 4 operation, and table 9.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 9.29 Example of Phase Counting Mode 4 Operation Table 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.6 Interrupts 9.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 8 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.7 Operation Timing 9.7.1 Input/Output Timing TCNT Count Timing: Figure 9.30 shows TCNT count timing in internal clock operation, and figure 9.31 shows TCNT count timing in external clock operation. φ Rising edge Falling edge Internal clock TCNT input clock TCNT N-1 N N+1 N+2 Figure 9.30 Count Timing in Internal Clock Operation φ External clock Rising edge Falling edge Falling edge TCNT input clock TCNT N-1 N N+1 Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.32 shows output compare output timing.
Section 9 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 9.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 9.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT N H'0000 N TGR Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 9.36 and 9.37 show the timing in buffer operation. φ n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 9.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 9.37 Buffer Operation Timing (Input Capture) 9.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 9.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 9.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 9.39 TGI Interrupt Timing (Input Capture) Rev.7.00 Dec.
Section 9 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 9.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 9.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figure 9.43 shows the timing for status flag clearing by the DMAC. TSR write cycle T1 T2 φ Address TSR address Write signal Status flag Interrupt request signal Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) 9.8 Usage Notes Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.45 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 9.47 shows the timing in this case. TGR write cycle T1 T2 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9.48 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register N M N TGR Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.50 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 9.50 Contention between TGR Write and Input Capture Rev.7.00 Dec.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.51 shows the timing in this case. Buffer register write cycle T2 T1 φ Buffer register address Address Write signal Input capture signal TCNT N M TGR Buffer register N M Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.53 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCFV flag TCNT write data H'FFFF M Prohibited Figure 9.
Section 9 16-Bit Timer Pulse Unit (TPU) Rev.7.00 Dec.
Section 10 Watchdog Timer (WDT) Section 10 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 10.1. 10.
Section 10 Watchdog Timer (WDT) Internal reset signal* Interrupt control Clock Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Overflow WOVI (interrupt request signal) WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: When a sub-block is operating, φ will be φSUB.
Section 10 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 7 OVF 0 R/(W)* 6 WT/IT 0 R/W Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 10 Watchdog Timer (WDT) 10.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows.
Section 10 Watchdog Timer (WDT) 10.3 Operation 10.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal for this LSI is issued.
Section 10 Watchdog Timer (WDT) 10.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) With WDT, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. This timing is illustrated in figure 10.3. φ TCNT H'FF H'00 Overflow signal (internal signal) WOVF Internal reset signal 518 states (WDT0) Figure 10.3 Timing of WOVF Setting 10.3.
Section 10 Watchdog Timer (WDT) 10.3.4 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 10.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 10.5 Timing of OVF Setting 10.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
Section 10 Watchdog Timer (WDT) 10.5 Usage Notes 10.5.1 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 10.6 shows the format of data written to TCNT and TCSR.
Section 10 Watchdog Timer (WDT) Writing 0 to WOVF bit 15 8 7 H'A5 Address: H'FF76 0 H'00 Write to RSTE, RSTS bits 15 Address: H'FF76 8 7 H'5A 0 Write data Figure 10.7 Format of Data Written to RSTCSR (Example of WDT0) Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read by using the same method as for the general registers. TCSR, TCNT, and RSTCSR are allocated in addresses H'FF74, H'FF75, and H'FF77 respectively. 10.5.
Section 10 Watchdog Timer (WDT) 10.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2. 10.5.
Section 11 Realtime Clock (RTC) Section 11 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 11.1 shows the block diagram of the RTC. 11.
Section 11 Realtime Clock (RTC) 11.2 Input/Output Pin Table 11.1 shows the RTC input/output pin. Table 11.1 Pin Configuration Name Abbreviation I/O Function Clock output TMOW RTC divided clock output 11.3 Output Register Descriptions The RTC has the following registers.
Section 11 Realtime Clock (RTC) Bit Bit Name Initial Value* R/W Description 7 BSY — RTC Busy R This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 SC12 — R/W Counting Ten’s Position of Seconds 5 SC11 — R/W Counts on 0 to 5 for 60-second counting.
Section 11 Realtime Clock (RTC) 11.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. This register is initialized to H'00 by a STBY input or the RST bit in RTCCR1, but not initialized by a RES input. The setting range is either decimal 0 to 11 or 0 to 23 by the selection of the 12/24 bit in RTCCR1.
Section 11 Realtime Clock (RTC) 11.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. This register is initialized to H'00 by a STBY input or the RST bit in RTCCR1, but not initialized by a RES input. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Section 11 Realtime Clock (RTC) 11.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. Bits 7 to 5 of this register are initialized to H'00 by a STBY input or the RST bit in RTCCR1, but not initialized by a RES input. For the definition of time expression, see figure 11.2.
Section 11 Realtime Clock (RTC) 11.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. This register is initialized to H'00 by a STBY input or the RST bit in RTCCR1, but not initialized by a RES input. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs.
Section 11 Realtime Clock (RTC) 11.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. This register is initialized to H'08 by a STBY input or RES input. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 MHz is selected, the RTC is disabled and operates as an 8-bit free running counter.
Section 11 Realtime Clock (RTC) 11.3.8 Extended Module Stop Register (EXMDLSTP) EXMDLSTP controls the clock supply of the RTC and USB. Note: When reading pin states using the port D register (PORTD), after accessing EXMDLSTP (address range: H'FFFF40 to H'FFFF5F), you must perform a dummy read to the external address space (such as H'FFEF00 to H'FF7FF) outside the range H'FFFF40 to H'FFFF5F before reading PORTD.
Section 11 Realtime Clock (RTC) 11.4 Operation 11.4.1 Initial Settings of Registers after Power-On and Resetting Procedure The RTC registers that store second, minute, hour, day-of week, operating mode, and A.M./P.M. data are not reset by an STBY input. Therefore, all registers must be set to their initial values after power-on and STBY input. Figure 11.3 shows the initial setting and resetting procedures of the RTC.
Section 11 Realtime Clock (RTC) 11.4.2 Time Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 11.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
Section 11 Realtime Clock (RTC) 11.5 Interrupt Source The RTC interrupt sources are listed in table 11.2. There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers (include ISCRH and IER of interrupt controller) are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1.
Section 11 Realtime Clock (RTC) Set IRQ5SCB = 0 and IRQ5SCA = 1 in ISCRH register Set the falling edge of IRQ5 Read ISR register Clear the IRQ5F flag Write 0 to bit 5 in ISR register Set RTC register Write 1 to bit 5 in IER IRQ5 is enabled RUN in RTCCR1 = 1 Figure 11.5 Initializing Procedure in Using RTC Interrupt Read ISR register Clear the IRQ5F flag Write 0 to bit 5 in ISR register Interrupt handling RTE Figure 11.6 Example of RTC Interrupt Handling Routine 11.
Section 11 Realtime Clock (RTC) Table 11.
Section 12 Serial Communication Interface Section 12 Serial Communication Interface This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Section 12 Serial Communication Interface • Average transfer rate generator (SCI_0): 921.569 kbps, 720 kbps, 460.784 kbps, or 115.196 kbps can be selected at 16 MHz 921.053 kbps, 720 kbps, 460.526 kbps, or 115.
Section 12 Serial Communication Interface 12.1.1 Block Diagram Module data bus RxD0 RDR TDR RSR TSR PG1/IRQ7 Parity generation Parity check BRR SCMR SSR SCR SMR SEMRA_0 SEMRB_0 control transmission and reception TxD0 Internal data bus Bus interface Figure 12.1 shows the block diagram of the SCI_0. Figure 12.2 shows the block diagram of the SCI_2.
Module data bus TDR RDR SCMR BRR SSR φ SCR RxD RSR TSR Baud rate generator SMR φ/16 control transmission and reception TxD Detecting parity φ/4 φ/64 Clock Parity check External clock SCK Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart card register BRR: Bit rate register Figure 12.2 Block Diagram of SCI_2 Rev.7.00 Dec.
Section 12 Serial Communication Interface 12.2 Input/Output Pins Table 12.1 shows the serial pins for each SCI channel. Table 12.
Section 12 Serial Communication Interface 12.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 12.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
Section 12 Serial Communication Interface 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 MP R/W Multiprocessor Mode (enabled only in asynchronous mode) 0 When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. For details, see section 12.5, Multi Processor Communication Function. 1 CKS1 0 R/W Clock Select 0 and 1: 0 CKS0 0 R/W These bits select the clock source for the baud rate generator.
Section 12 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W 6 BLK 0 R/W GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see section 12.7.9, Clock Output Control. 0: Normal smart card interface mode operation (initial value) (1) The TEND flag is generated 12.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 5 PE R/W Parity Enable 0 When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 12.7.
Section 12 Serial Communication Interface 12.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 12.9, Interrupts. Some bits in SCR have different functions in normal mode and smart card interface mode.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 MPIE R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) 0 When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 12 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name Initial Value TIE 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RERF, FER, and ORER flags in SSR, are not performed.
Section 12 Serial Communication Interface 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Section 12 Serial Communication Interface Bit 5 Bit Name Initial Value R/W ORER 0 Description 1 R/(W)* Overrun Error [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
Section 12 Serial Communication Interface Bit 3 Bit Name Initial Value R/W PER 0 Description 1 R/(W)* Parity Error [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
Section 12 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name Initial Value R/W TDRE 1 Description 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 12 Serial Communication Interface Bit 5 Bit Name Initial Value R/W ORER 0 Description 1 R/(W)* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial cannot be continued while the ORER flag is set to 1.
Section 12 Serial Communication Interface Bit 3 Bit Name Initial Value R/W PER 0 Description 1 R/(W)* Parity Error Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 1 MPB 0 R Multiprocessor Bit 0 MPBT 0 R/W Multiprocessor Bit Transfer This bit is not used in Smart Card interface mode. Write 0 to this bit in Smart Card interface mode. Note: 1. The write value should always be 0 to clear the flag. 2. To clear the flag by the CPU on the HD6432210S, reread the flag after writing 0 to it. 12.3.
Section 12 Serial Communication Interface 12.3.9 Serial Extended Mode Register A_0 (SEMRA_0) SEMRA_0 extends the functions of SCI_0. SEMR0 enables selection of the SCI_0 select function in synchronous mode, base clock setting in asynchronous mode, and also clock source selection and automatic transfer rate setting. Figure 12.3 shows an example of the internal base clock when an average transfer rate is selected and figure 12.4 shows as example of the setting when the TPU clock input is selected.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 ABCS 0 R/W Asynchronous Base Clock Select Selects the 1-bit-interval base clock in asynchronous mode. The ABCS setting is valid in asynchronous mode (C/A = 0 in SMR).
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 ACS2 0 1 ACS1 0 0 ACS0 0 R/W 0101: 115.196 kbps average transfer rate (for φ = 16 MHz only) is selected (SCI_0 operates on base clock with R/W frequency of 16 times transfer rate) R/W 0110: 460.
Section 12 Serial Communication Interface Bit Bit Name Initial Value R/W Description 7 ACS3 R/W Asynchronous Clock Source Select 0 Selects the clock source in asynchronous mode depending on the combination with the ACS2 to ACS0 (bits 2 to 0 in SEMRA_0). For details, see section 12.3.9, Serial Extended Mode Register A_0 (SEMRA_0). 6 to 4 — Undefined 3 TIOCA2E 1 — Reserved The write value should always be 0. R/W TIOCA2 Output Enable Controls the TIOCA2 output on the P16 pin.
Rev.7.00 Dec. 24, 2008 Page 388 of 698 REJ09B0074-0700 1.8424 MHz 4 5 6 7 8 9 10 11 12 Average transfer rate = 1.8424 MHz/16 = 115.152 kbps Average error with 115.2 kbps = -0.043% 1 bit = Base clock × 16* 1 2 3 2.667 MHz 15 16 1 bit = base clock × 8* 3.6848 MHz 4 5 6 7 8 Average transfer rate = 3.6848 MHz/8 = 460.606 kbps Average error with 460.6 kbps = -0.043% 1 2 3 5.
2 2 3 3 4 5 4 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 1 bit = base clock × 16* 1.8431 MHz 5 6 7 8 2 MHz Average transfer rate = 1.8431 MHz/16 = 115.196 kbps Average error with 115.2 kbps = -0.004% 1 1 2 2 3 3 4 5 4 6 7 8 9 10 11 12 13 14 15 16 2 2 4 5 6 7 8 5.
6 7 8 9 1 bit = base clock × 16* 1.8421 MHz 2 3 4 5 10 11 Average transfer rate =1.8421 MHz/16 = 115.132 kbps Average error with 115.2 kbps = -0.0059% 1 3 MHz 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 Rev.7.00 Dec. 24, 2008 Page 390 of 698 REJ09B0074-0700 6 7 8 9 1 bit = base clock × 16* 7.3684 MHz 2 3 4 5 1 5 6 1 bit = base clock × 8* 5.
SCK0 Base clock = 4 MHz × 3/4 = 3 MHz (Average) Clock enable TIOCA2 output Base clock TIOCA1output = 4 MHz 3 MHz 3 4 MHz 3 3 4 4 1 1 5 2 2 6 3 3 4 Average transfer rate = 3 MHz/16 = 187.5 kbps 1 bit = Base clock × 16* 2 2 2 7 1 1 8 2 2 9 3 3 Note: * The lengh of one bit varies according to the base clock synchronization.
Rev.7.00 Dec. 24, 2008 Page 392 of 698 REJ09B0074-0700 SCK0 Base clock = 9.6 MHz × 15/16 = 9 MHz (Average) Clock enable TIOCA1 output Base clock (TIOCA0 + TIOCC0) output = 9.6 MHz TIOCC0 output = 4.8 MHz TIOCA0 output = 4.8 MHz 5 5 9 MHz 4 5 9.6 MHz 4 4 6 6 6 7 7 7 8 8 8 1 bit = Base clock × 16* 3 3 3 9 9 9 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 16 Average transfer rate = 9 MHz/16 = 562.
SCK0 Base clock = 6 MHz × 23/25 = 5.52 MHz (Average) 25 1 1 1 2 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 11 12 10 11 12 10 11 12 13 Average transfer rate = 5.52 MHz/16 = 345 kbps 1 bit = Base clock × 16* 4 6 MHz 3 4 5.52 MHz 2 3 2 3 13 13 14 15 16 1 2 3 4 24 25 5 6 7 1 TCLKB TCLKA TIOCA0 TIOCC0 TIOCA1 TIOCA2 TPU 21 22 23 21 22 23 18 19 20 18 19 20 14 15 16 17 14 15 16 17 Note: * The length of one bit varies according to the base clock synchronization.
Rev.7.00 Dec. 24, 2008 Page 394 of 698 REJ09B0074-0700 SCK0 Base clock = 9.6 MHz × 23/25 = 8.832 MHz (Average) Clock enable (TIOCA1×TIOCA2) output TIOCA2 output TIOCA1 output Base clock (TIOCA0 + TIOCC0) output = 9.6 MHz TIOCC0 output = 4.8 MHz TIOCA0 output = 4.8 MHz 5 5 6 6 8.832 MHz 4 5 6 9.
Section 12 Serial Communication Interface 12.3.11 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Section 12 Serial Communication Interface Timing and Reception Margin. Tables 12.5 and 12.7 show the maximum bit rates with external clock input. When the ABCS bit in SCI_0’s serial extended mode register A_0 (SEMRA_0) is set to 1 in asynchronous mode, the maximum bit rates are twice those shown in table 12.3. Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 2 2.097152 Bit Rate (bps) n N Error (%) n N 110 1 141 0.03 1 150 1 103 0.
Section 12 Serial Communication Interface Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.
Section 12 Serial Communication Interface Operating Frequency φ (MHz) 9.8304 Bit Rate (bps) n N 110 2 150 Error (%) 10 12 12.288 n N Error (%) n N Error (%) n N Error (%) 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.
Section 12 Serial Communication Interface Operating Frequency φ (MHz) 18 Bit Rate (bps) n N 110 3 79 150 2 300 19.6608 Error (%) –0.12 n N 20 Error (%) n N 24 Error (%) n N Error (%) 3 86 0.31 3 88 –0.25 3 106 –0.44 233 0.16 2 255 0.00 3 64 0.16 3 77 0.16 2 116 0.16 2 127 0.00 2 129 0.16 2 155 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 2 77 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 1 155 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.
Section 12 Serial Communication Interface Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (kbps) ABCS = 0 ABCS = 1 φ (MHz) Maximum Bit Rate External (kbps) Input Clock (MHz) ABCS = 0 ABCS = 1 2 0.5000 31.25 62.5 9.8304 2.4576 153.6 307.2 2.097152 0.5243 327.68 65.536 10 2.5000 156.25 312.5 2.4576 0.6144 38.4 76.8 12 3.0000 187.5 375.0 3 0.7500 46.875 93.75 12.288 3.0720 192.0 384.0 3.6864 0.
Section 12 Serial Communication Interface Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate 2 4 6 (bps) n N n N 110 3 70 — — 250 2 124 2 249 n N 8 10 16 n N n N n N 3 124 — — 3 249 20 n N 24 n N — 500 1 249 2 124 2 249 — — 3 124 — — — 1k 1 124 1 249 2 124 — — 2 249 — — — — 2.
Section 12 Serial Communication Interface Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, when n = 0 and S = 372) Operating Frequency φ (MHz) 5.00 7.00 7.1424 10.00 10.7136 13.00 Bit Rate (bps) N Error (%) N Error (%) N Error (%) N Error (%) N Error (%) N Error (%) 6720 0 0.01 1 30.00 1 28.57 1 0.01 1 7.14 2 13.33 9600 0 30.00 0 1.99 0 0.00 1 30.00 1 25.00 1 8.99 Operating Frequency φ (MHz) 14.2848 16.00 18.00 20.00 Error (%) 24.
Section 12 Serial Communication Interface 12.4 Operation in Asynchronous Mode Figure 12.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line.
Section 12 Serial Communication Interface 12.4.1 Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function. Table 12.
Section 12 Serial Communication Interface 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in Figure 12.6.
Section 12 Serial Communication Interface Note: * Figure 12.6 shows an example when the ABCS bit of SEMRA_0 is cleared to 0. When ABCS is set to 1, the clock frequency of basic clock is 8 times the bit rate and the receive data is sampled at the rising edge of the 4th pulse of the basic clock. 12.4.
Section 12 Serial Communication Interface 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.8. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 12 Serial Communication Interface 12.4.5 Data Transmission (Asynchronous Mode) Figure 12.9 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 12 Serial Communication Interface Initialization [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 12 Serial Communication Interface 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.11 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 12 Serial Communication Interface Table 12.
Section 12 Serial Communication Interface [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No Clear RE bit in SCR to 0 PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.12 Sample Serial Data Reception Flowchart (2) Rev.7.00 Dec.
Section 12 Serial Communication Interface 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 12 Serial Communication Interface Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB = 1) Legend: MPB: Multiprocessor bit ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Figure 12.
Section 12 Serial Communication Interface 12.5.1 Multiprocessor Serial Data Transmission Figure 12.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Section 12 Serial Communication Interface 12.5.2 Multiprocessor Serial Data Reception Figure 12.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.
Section 12 Serial Communication Interface Initialization Start reception Read MPIE bit in SCR [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 12 Serial Communication Interface [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.16 Sample Multiprocessor Serial Data Reception Flowchart (2) Rev.7.00 Dec.
Section 12 Serial Communication Interface 12.6 Operation in Clocked Synchronous Mode Figure 12.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock.
Section 12 Serial Communication Interface 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 12.18. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 12 Serial Communication Interface 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.19 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
Section 12 Serial Communication Interface Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.19 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev.7.00 Dec.
Section 12 Serial Communication Interface Initialization [1] Start transmission Read TDRE flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 12 Serial Communication Interface 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2.
Section 12 Serial Communication Interface Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1.
Section 12 Serial Communication Interface Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt.
Section 12 Serial Communication Interface 12.7 Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 12.7.1 Pin Connection Example Figure 12.24 shows an example of connection with the Smart Card.
Section 12 Serial Communication Interface 12.7.2 Data Format (Except for Block Transfer Mode) Figure 12.25 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
Section 12 Serial Communication Interface bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State Figure 12.27 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F.
Section 12 Serial Communication Interface 12.7.5 Receive Data Sampling Timing and Reception Margin In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0.
Section 12 Serial Communication Interface 12.7.6 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. 2. 3. 4. Clear the TE and RE bits in SCR to 0. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR.
Section 12 Serial Communication Interface 12.7.7 Serial Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 12.29 illustrates the retransfer operation when the SCI is in transmit mode. 1.
Section 12 Serial Communication Interface nth transfer frame Transfer frame n + 1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND FER/ERS Figure 12.29 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 12.30.
Section 12 Serial Communication Interface Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 12.31 Example of Transmission Processing Flow Rev.7.00 Dec.
Section 12 Serial Communication Interface 12.7.8 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 12.32 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated.
Section 12 Serial Communication Interface Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 12.33 Example of Reception Processing Flow 12.7.9 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 12.
Section 12 Serial Communication Interface When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2.
Section 12 Serial Communication Interface 12.8 SCI Select Function (Clocked Synchronous Mode) The SCI_0 supports the SCI select function which allows clock synchronous communication between master LSI and one of multiple slave LSI. Figure 12.36 shows an example of communication using the SCI select function. Figure 12.37 shows the operation. The master LSI can communicate with slave LSI_A by bringing SEL_A and SEL_B signals low and high, respectively.
Section 12 Serial Communication Interface Communication between master LSI Communication between master LSI and slave LSI_A and slave LSI_B Period of M_SCK = high [Master LSI] M_SCK M_TxD D0 D1 D7 D0 D1 D7 M_RxD D0 D1 D7 D0 D1 D7 SEL_A SEL_B [Slave LSI_A] IRQ7_A (SEL_A) SCK0_A Fixed high level RSR0_A TxD0_A D0 Hi-Z D0 D6 D1 D7 Hi-Z D7 [Slave LSI_B] IRQ7_B (SEL_B) Fixed high level SCK0_B RSR0_B TxD0_B D0 Hi-Z D0 D6 D1 D7 D7 Hi-Z Figure 12.
Section 12 Serial Communication Interface 12.9 Interrupts 12.9.1 Interrupts in Normal Serial Communication Interface Mode Table 12.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Section 12 Serial Communication Interface 12.9.2 Interrupts in Smart Card Interface Mode Table 12.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Note: In case of block transfer mode, see section 12.9.1, Interrupts in Normal Serial Communication Interface Mode. Table 12.
Section 12 Serial Communication Interface 12.10.3 Mark State and Break Detection (Asynchronous Mode Only) When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1.
Section 12 Serial Communication Interface 12.10.6 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset.
Section 12 Serial Communication Interface No All data transmitted? [1] [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0. Yes Read TEND flag in SSR [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. No TEND = 1 [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode.
Section 12 Serial Communication Interface Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Final TxD bit retention High output Port SCI TxD output Port input/output Port High output* SCI TxD output Note: * Initialized by the software standby. Figure 12.41 Port Pin State of Synchronous Transmission Using Internal Clock Rev.7.00 Dec.
Section 12 Serial Communication Interface • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception.
Section 12 Serial Communication Interface 12.10.7 Switching from SCK Pin Function to Port Pin Function: When switching the SCK pin function to the output port function (high-level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. 2. 3. 4. End of serial data transmission TE bit = 0 C/A bit = 0 ... switchover to port output Occurrence of low-level output (see figure 12.
Section 12 Serial Communication Interface Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. 2. 3. 4. 5. End of serial data transmission TE bit = 0 CKE1 bit = 1 C/A bit = 0 ...
Section 13 Boundary Scan Function Section 13 Boundary Scan Function The HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU incorporate a boundary scan function, which is a serial I/O interface based on the JTAG (Joint Test Action Group, IEEEStd.1149.1 and IEEE Standard Test Access Port and Boundary Scan Architecture). Figure 13.1 shows the block diagram of the boundary scan function. 13.
Section 13 Boundary Scan Function BSCANR (Boundary scan cell chain) IDCODE MUX MUX BYPASS TDI INSTR TCK TMS TAP controller TRST Legend: BSCANR: IDCODE: BYPASS: INSTR: TAP: Boundary scan register IDCODE register BYPASS register Instruction register Test access port Figure 13.1 Block Diagram of Boundary Scan Function Rev.7.00 Dec.
Section 13 Boundary Scan Function 13.2 Pin Configuration Table 13.1 shows the I/O pins used in the boundary scan function. Table 13.1 Pin Configuration Pin Name I/O Function TMS Input Test Mode Select Controls the TAP controller which is a 16-state Finite State Machine. The TMS input value at the rising edge of TCK determines the status transition direction on the TAP controller. The TMS is fixed high when the boundary scan function is not used. The protocol is based on JTAG standard (IEEE Std.1149.
Section 13 Boundary Scan Function 13.3 Register Descriptions The boundary scan function has the following registers. These registers cannot be accessed by the CPU. • • • • Instruction register (INSTR) IDCODE register (IDCODE) BYPASS register (BYPASS) Boundary scan register (BSCANR) 13.3.1 Instruction Register (INSTR) INSTR is a 3-bit register. At initialization, this register is specified to IDCODE mode.
Section 13 Boundary Scan Function EXTEST: The EXTEST instruction is used to test external circuits when this LSI is installed on the print circuit board. If this instruction is executed, output pins are used to output test data (specified by the SAMPLE/PRELOAD instruction) from the boundary scan register to the print circuit board, and input pins are used to input test results.
Section 13 Boundary Scan Function 13.3.2 IDCODE Register (IDCODE) IDCODE register is a 32-bit register. If INSTR is set to IDCODE mode, IDCODE is connected between TDI and TDO. The HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU output fixed codes H'002A200F from the TDO. Serial data cannot be written to IDCODE register through TDI. Table 13.3 shows the IDCODE register configuration. Table 13.
Section 13 Boundary Scan Function TDI pin IN Control I/O pin OUT TDO pin Figure 13.2 Boundary Scan Register Configuration Table 13.4 Correspondence between LSI Pins and Boundary Scan Register TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No. Pin Name I/O Bit Name 96 D5 PF1/BACK IN 180 Control 179 OUT 178 IN 177 Control 176 OUT 175 IN 174 Control 173 97 98 99 100 1 2 3 4 5 B4 A3 C4 B3 B2 B1 D4 C2 C1 PF0/BREQ/IRQ2 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 Rev.7.00 Dec.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No. Pin Name I/O Bit Name 55 H9 P74/MRES IN 60 Control 59 OUT 58 IN 57 Control 56 OUT 55 56 H10 P71/CS5 57 H11 STBY IN 54 58 G8 RES IN 53 63 F11 P70/CS4 IN 52 Control 51 OUT 50 IN 49 Control 48 OUT 47 IN 46 Control 45 64 65 66 67 68 69 F10 F8 E11 E10 E9 D11 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 Rev.7.00 Dec.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No.
Section 13 Boundary Scan Function TFP-100G TFP-100GV Pin No. BP-112 BP-112V Pin No. Pin Name 80 A9 81 C8 I/O Bit Name FWE IN 1 NMI IN 0 to TDO 13.4 Boundary Scan Function Operation 13.4.1 TAP Controller Figure 13.3 shows the TAP controller status transition diagram, based on the JTAG standard.
Section 13 Boundary Scan Function 13.5 Usage Notes 1. When using the boundary scan function, clear TRST to 0 at power-on and after the tRESW time has elapsed set TRST to 1 and set TCK, TMS, and TDI appropriately. During normal operation when the boundary scan function is not used, set TCK, TMS, and TDI to Hi-Z, clear TRST to 0 at power-on, and after the tRESW time has elapsed set TRST to 1 or to Hi-Z.
Section 13 Boundary Scan Function 5. If a pin with pull-up function is SAMPLEed with pull-up function enabled, the corresponding IN register is set to 1. In this case, the corresponding Control register must be cleared to 0. 6. If a pin with open-drain function is SAMPLEed while its open-drain function is enabled and while the corresponding OUT register is set to 1, the corresponding Control register is cleared to 0 (the pin status is Hi-Z).
Section 14 Universal Serial Bus (USB) Section 14 Universal Serial Bus (USB) This LSI incorporates a USB function module complying with USB standard version 1.1. Figure 14.1 shows the block diagram of the USB. 14.1 Features • USB standard version 2.
Section 14 Universal Serial Bus (USB) Note: In this section, power-down mode represents watch, subactive, subsleep, and software standby modes.
Section 14 Universal Serial Bus (USB) 14.2 Input/Output Pins Table 14.1 shows the USB pin configuration. Table 14.1 Pin Configuration Pin Name I/O Function USD+ I/O I/O pin for USB data DrVCC Input USB internal transceiver power supply pin DrVSS Input USB internal transceiver ground pin VBUS Input USB cable connection/disconnection detection signal pin UBPM Input USB bus-powered/self-powered mode set pin USD- When USB is used in bus-powered mode, UBPM must be fixed low.
Section 14 Universal Serial Bus (USB) • • • • • • • • • • • • • • • • USB interrupt flag register 0 (UIFR0) USB interrupt flag register 1 (UIFR1) USB interrupt flag register 3 (UIFR3) USB interrupt enable register 0 (UIER0) USB interrupt enable register 1 (UIER1) USB interrupt enable register 3 (UIER3) USB interrupt select register 0 (UISR0) USB interrupt select register 1 (UISR1) USB interrupt select register 3 (UISR3) USB data status register (UDSR) USB Configuration value register (UCVR) USB test regis
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W Description 5 UCKS3 0 USB Operation Clock Select 3 to 0 4 UCKS2 3 UCKS1 2 UCKS0 R/W These bits control the on-chip PLL, which generates the USB operation clock (48 MHz). When UCKS3 to UCKS0 are 0000, the PLL circuit stops and thus the USB operation clock must be selected according to the clock source. The on-chip PLL circuit starts operating after the USB module stop 2 bit has been cancelled.
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W Description 1 UIFRST 1 USB Interface Software Reset R/W Controls USB module internal reset. When the UIFRST bit is set to 1, the USB internal modules other than UCTLR, UIER3, and the CK48READY bit in UIFR3 are all reset. At initialization, the UIFRST bit must be cleared to 0 after the USB operating clock (48 MHz) stabilization time has passed following the clearing of the USB module stop 2 bit.
Section 14 Universal Serial Bus (USB) 14.3.2 USB DMAC Transfer Request Register (UDMAR) UDMAR is set when data transfer by means of a USB request of the on-chip DMAC is performed for data registers UEDR1 and UEDR2 corresponding to EP1 and EP2 respectively used for Bulk transfer. For the DMAC transfer, set DREQ0 and DREQ1 separately. If DREQ0 and DREQ1 usage overlaps, the USB cannot operate correctly. For details on DMAC transfer, refer to section 14.6, DMA Transfer Specifications.
Section 14 Universal Serial Bus (USB) 14.3.3 USB Device Resume Register (UDRR) UDRR indicates the enabled or disabled state of remote wakeup by the host, and executes the remote wakeup of the USB modules in the suspend state. Bit Bit Name 7 to 2 — Initial Value R/W Description All 0 Reserved R These bits are always read as 0 and cannot be modified. 1 RWUPs 0 R Remote Wakeup Status Indicates the enabled or disabled state of remote wakeup by the host.
Section 14 Universal Serial Bus (USB) 14.3.4 USB Trigger Register 0 (UTRG0) UTRG0 is a one-shot register to generate triggers to the FIFO for each endpoint EP0 to EP3. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 R Reserved These bits are always read as 0 and cannot be modified. 5 EP2RDFN 0 W EP2 Read Complete 0: Performs no operation. 1: Writes 1 to this bit after reading data for EP2 OUT FIFO.
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W 0 EP0sRDFN 0 W Rev.7.00 Dec. 24, 2008 Page 474 of 698 REJ09B0074-0700 Description EP0s Read Complete 0: Performs no operation. A NAK handshake is returned in response to transmit/receive requests in the data stage until 1 is written to this bit. 1: Writes 1 to this bit after reading data for EP0s command FIFO. After receiving the setup command, this trigger enables the next packet in the data stage to be received by EP0i and EP0o.
Section 14 Universal Serial Bus (USB) 14.3.5 USB FIFO Clear Register 0 (UFCLR0) UFCLR0 is a one-shot register used to clear the FIFO for each endpoint EP0 to EP3. Writing 1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR0 clears the data for which the corresponding PKTE bit in UTRG0 is not set to 1 after data write, or data that is validated by setting the corresponding PKTE bit in UTRG0.
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W Description 0 — 0 Reserved R This bit is always read as 0 and cannot be modified. Note:* When DMA writes are enabled (EP2T1 set to 1 and EP2T0 set to 0 or 1 in UDMAR), it is not possible to clear the data in the FIFO by writing 1 to EP2CLR. To clear the data in the FIFO, disable DMA transfers (clear EP2T1 and EP2T0 in UDMAR to 0) and then write 1 to EP2CLR. 14.3.
Section 14 Universal Serial Bus (USB) 14.3.7 USB Endpoint Stall Register 1 (UESTL1) UESTL1 is used to control stall cancellation mode for all endpoints. Bit Bit Name Initial Value R/W Description 7 SCME 0 Reserved R/W The write value should always be 0. 6 to 0 14.3.8 — All 0 R Reserved These bits are always read as 0 and cannot be modified. USB Endpoint Data Register 0s (UEDR0s) UEDR0s stores the setup command for endpoint 0 (for Control_out transfer).
Section 14 Universal Serial Bus (USB) 14.3.10 USB Endpoint Data Register 0o (UEDR0o) UEDR0o is a data register for endpoint 0 (for Control_out transfer). UEDR0o stores data received from the host. The number of data items to be read must be the number of bytes specified by UESZ0o. When 1 byte is read from UEDR0o, UESZ0o is decremented by1. UEDR0o is a byte register to which 4-byte address area is assigned.
Section 14 Universal Serial Bus (USB) 14.3.13 USB Endpoint Data Register 2 (UEDR2) UEDR2 is a data register for endpoint 2 (for Bulk_out transfer). UEDR2 stores data received from the host. The number of data items to be read must be the number of bytes specified by UESZ2. When 1 byte is read from UEDR2, UESZ2 is decremented by1. UEDR2 is a byte register to which 4-byte address area is assigned.
Section 14 Universal Serial Bus (USB) 14.3.16 USB Interrupt Flag Register 0 (UIFR0) UIFR0 is an interrupt flag register indicating the setup command reception, EP0 and EP3 transmission/reception, and bus reset state. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. A bit in this register can be cleared by writing 0 to it. Writing 1 to a bit is invalid and causes no operation.
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W 7 BRST 0 Description R/(W)* Bus Reset Set to 1 when the bus reset signal is detected on the USB bus. The corresponding interrupt output is EXIRQ0 or EXIRQ1. Note that BRST is also set to 1 if D+ is not pulled-up during USB cable connection. 6 — 0 R Reserved This bit is always read as 0 and cannot be modified.
Section 14 Universal Serial Bus (USB) 14.3.17 USB Interrupt Flag Register 1 (UIFR1) UIFR1 is an interrupt flag register indicating the EP1 and EP2 status. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP1TR flags can be cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation. Consequently, to clear a flag, write 0 to the corresponding bit and 1 to all the other bits. (For example, write H'FD to clear bit 1.
Section 14 Universal Serial Bus (USB) 14.3.18 USB Interrupt Flag Register 3 (UIFR3) UIFR3 is an interrupt flag register indicating the USB status. If the corresponding bit is set to 1, the corresponding EXIRQ0, EXIRQ1, or IRQ6 interrupt is requested to the CPU. VBUSi, SPRSi, SETC, SOF, and CK48READY flags can be cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation. Consequently, to clear a flag, write 0 to the corresponding bit and 1 to all the other bits.
Section 14 Universal Serial Bus (USB) Bit Bit Name Initial Value R/W 2 SPRSi 0 Description R/(W)* Suspend/Resume Interrupt Set to 1 if a transition from normal state to suspend state or suspend state to normal state has occurred. The corresponding interrupt output is IRQ6. This bit can be used to cancel power-down mode at resuming. 1 VBUSs 0 R VBUS Status VBUSs is a status bit to indicate the VBUS state by the USB cable connection or disconnection.
Section 14 Universal Serial Bus (USB) 14.3.20 USB Interrupt Enable Register 1 (UIER1) UIER1 enables the interrupt request indicated in the interrupt flag register 1 (UIFR1). When an interrupt flag is set while the corresponding bit in UIER1 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1. Either EXIRQ0 or EXIRQ1 must be selected by the interrupt select register 1 (UISR1).
Section 14 Universal Serial Bus (USB) 14.3.22 USB Interrupt Select Register 0 (UISR0) UISR0 sets EXIRQ to output interrupt request indicated in the interrupt flag register 0 (UIFR0). When a bit in UIER0 corresponding to the UISR0 bit is cleared to 0, an interrupt request is output from EXIRQ0. When a bit in UIER0 corresponding to the UISR0 bit is set to 1, an interrupt request is output from EXIRQ1. Bit Bit Name Initial Value R/W Description 7 BRSTS 0 R/W Selects the BRST interrupt.
Section 14 Universal Serial Bus (USB) 14.3.24 USB Interrupt Select Register 3 (UISR3) UISR3 sets EXIRQ to output interrupt request indicated in the interrupt flag register 3 (UIFR3). When a bit in UIER3 corresponding to the UISR3 bit is cleared to 0, an interrupt request is output from EXIRQ0. When a bit in UIER3 corresponding to the UISR3 bit is set to 1, an interrupt request is output from EXIRQ1. Bit Bit Name 7 CK48READYS 0 R/W Selects the CK48READY interrupt.
Section 14 Universal Serial Bus (USB) Bit Bit Name 7 to 3 — Initial Value R/W Description All 0 Reserved R These bits are always read as 0 and cannot be modified. 2 EP1DE 0 R EP1 Data Enable 0: Indicates that the EP1 contains no valid data. 1: Indicates that the EP1 contains valid data. EP1DE corresponds to the negative-electrode signal for EP1ALLEMPTYs in UIFR1. 1 EP3DE 0 R EP3 Data Enable 0: Indicates that the EP3 contains no valid data. 1: Indicates that the EP3 contains valid data.
Section 14 Universal Serial Bus (USB) 14.3.27 USB Test Register 0 (UTSTR0) UTSTR0 controls the on-chip transceiver output signals. Setting the PTSTE bit to 1 after setting UIFRST and UDCRST in UCTLR to 0 specifies the transceiver output signals (USD+ and USD-) arbitrarily. Table 14.2 shows the relationship between UTSTR0 setting and pin output.
Section 14 Universal Serial Bus (USB) Table 14.2 Relationship between UTSTR0 Setting and Pin Output Register Setting Pin Output UCTLR/ Pin Input Register Setting Pin Output USPND/ TMOWE PTSTE SUSPEND TMOW VBUS PTSTE OE FSE0 VPO USD+ USD- 1 × × — 0 × × × × Hi-Z Hi-Z 0 0 × — 1 0 × × × — — 0 1 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 × 0 0 1 1 1 × × Hi-Z Hi-Z Legend: ×: Don’t care —: Cannot be controlled.
Section 14 Universal Serial Bus (USB) Table 14.
Section 14 Universal Serial Bus (USB) 14.3.29 USB Test Registers 2 and A to F (UTSTR2, UTSTRA to UTSTRF) UTSTR2 and UTSRTA to UTSRTF are test registers and cannot be written to. 14.3.30 Module Stop Control Register B (MSTPCRB) Bit Bit Name Initial Value R/W Description 7 MSTPB7 1 R/W Module Stop 6 MSTPB6 1 5 MSTPB5 1 4 MSTPB4 1 3 MSTPB3 1 2 MSTPB2 1 1 MSTPB1 1 0 MSTPB0 1 For details, refer to section 20.1.3, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
Section 14 Universal Serial Bus (USB) 14.3.31 Extended Module Stop Register (EXMDLSTP) Bit Bit Name 7 to 2 — Initial Value R/W Description Undefined — Reserved These bits are always read as an undefined value and cannot be modified. 1 RTCSTOP 0 R/W RTC Module Stop 0: Cancels the RTC module stop. 1: Sets the RTC module stop. 0 USBSTOP1 0 R/W USB Module Stop 1 0: Cancels the stop state of the USB module partly. A clock is provided for the USB module partly.
Section 14 Universal Serial Bus (USB) 14.4 Interrupt Sources This module has three interrupt signals. Table 14.4 shows the interrupt sources and their corresponding interrupt request signals. The EXIRQ interrupt signals are activated at low level. The EXIRQ interrupt requests can only be detected at low level (specified as level sensitive). The suspend/resume interrupt request IRQ6 must be specified to be detected at the falling edge (fallingedge sensitive) by the interrupt controller register. Rev.7.
Section 14 Universal Serial Bus (USB) Table 14.
Section 14 Universal Serial Bus (USB) Register Bit UIFR3 0 1 Interrupt Request Signal DMAC Activation by USB 5 Request* Transfer Mode Interrupt Source Description ⎯ (Status) VBUSi VBUS interrupt EXIRQ0 or EXIRQ1 × (VBUSs) VBUS status × × 2 SPRSi Suspend/resume interrupt IRQ6 * 3 (SPRSs) Suspend/resume status × × 4 Reserved ⎯ ⎯ ⎯ 5 SETC Set_Configuration detection EXIRQ0 or EXIRQ1 × 6 SOF Start of Frame packet detection EXIRQ0 or EXIRQ1 × 7 CK48READY USB operating
Section 14 Universal Serial Bus (USB) 14.5 Communication Operation 14.5.1 Initialization The USB must be initialized as described in the flowchart in figure 14.2. USB function Firmware Cancel power-on reset Cancel USB module stop 1 (Clear USBSTP1 in EXMDLSTP to 0) Start USB operationg clock oscillation.
Section 14 Universal Serial Bus (USB) 14.5.2 USB Cable Connection/Disconnection (1) USB Cable Connection (When USB module stop or power-down mode is not used) If the USB cable enters the connection state from the disconnection state in an application (self powered) where USB module stop or power-down mode is not used, perform the operation as shown in figure 14.3. In bus-powered mode, perform the operation according to note 2 in figure 14.3.
Section 14 Universal Serial Bus (USB) (2) USB Cable Connection (When USB module stop or power-down mode is used) If the USB cable enters the connection state from the disconnection state in an application (self powered) where USB module stop or power-down mode is used, perform the operation as shown in figure 14.4.
Section 14 Universal Serial Bus (USB) (3) USB Cable Disconnection (When USB module stop or power-down mode is not used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or power-down mode is not used, perform the operation as shown in figure 14.5. In bus-powered mode, the power is automatically turned off when the USB cable is disconnected and the following processing is not required.
Section 14 Universal Serial Bus (USB) (4) USB Cable Disconnection (When USB module stop or power-down mode is used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or power-down mode is used, perform the operation as shown in figure 14.6.
Section 14 Universal Serial Bus (USB) 14.5.3 Suspend and Resume Operations (1) Suspend and Resume Operations Figures 14.7 and 14.8 are flowcharts of the suspend and resume operations. If the USB bus enters the suspend state from a non-suspend state, or if it enters a non-suspend state from the suspend state due to a resume signal from up-stream, perform the operations shown below.
Section 14 Universal Serial Bus (USB) (2) Suspend and Resume Interrupt Processing Figure 14.8 is a flowchart of suspend and resume interrupt processing.
Section 14 Universal Serial Bus (USB) (3) Suspend and Remote-Wakeup Operations Figures 14.9 and 14.10 are flowcharts of the suspend and remote-wakeup operations. If the USB bus enters a non-suspend state from the suspend state due to a remote-wakeup signal from this function, perform the operations shown below.
Section 14 Universal Serial Bus (USB) (4) Remote-Wakeup Interrupt Processing Figure 14.10 is a flowchart of remote-wakeup interrupt processing.
Section 14 Universal Serial Bus (USB) 14.5.4 Control Transfer The control transfer consists of three stages; setup, data (sometimes omitted), and status, as shown in figure 14.11. The data stage consists of multiple bus transactions. Figures 14.12 to 14.16 show operation flows in each stage. Setup stage Control-in Control-out No data Data stage SETUP (0) IN (1) IN (0) DATA0 DATA1 DATA0 SETUP (0) OUT (1) OUT (0) DATA0 DATA1 DATA0 Status stage ... ...
Section 14 Universal Serial Bus (USB) (1) Setup Stage USB function Firmware Receive SETUP token Receive 8-byte command data in UEDR0s Command to be processed by firmware? No Automatic processing by this module Yes Set setup command recive complete flag (SetupTS in UIFR0 = 1) To data stage EXIRQx Clear SetupTS flag (SetupTS in UIFR0 = 0) Clear EP0i FIFO (EP0iCLR in UFCLR = 1) Clear EP0o FIFO (EP0oCLR in UFCLR = 1) Read 8-byte data from UEDR0s Decode command data Determine data stage direction*1
Section 14 Universal Serial Bus (USB) (2) Data Stage (Control-In) The firmware first analyzes the command data that is sent from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS in UIFR0 is set to 1).
Section 14 Universal Serial Bus (USB) (3) Data Stage (Control-Out) The firmware first analyzes the command data that is sent from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is out-transfer, data from the host is waited for, and after data is received (EP0oTS in UIFR0 is set to 1), data is read from the FIFO.
Section 14 Universal Serial Bus (USB) (4) Status Stage (Control-In) The control-in status stage starts with an OUT token from the host. The firmware receives 0byte data from the host, and ends control transfer.
Section 14 Universal Serial Bus (USB) (5) Status Stage (Control-Out) The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The firmware recognizes from this interrupt that the status stage has started.
Section 14 Universal Serial Bus (USB) 14.5.
Section 14 Universal Serial Bus (USB) 14.5.6 Bulk-In Transfer (Dual FIFOs) (Endpoint 1) EP1 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being aware of this dual-FIFO configuration. However, one data write should be performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP1PKTE at one time after consecutively writing 128 bytes of data. EP1PKTE must be performed for each 64- byte write.
Section 14 Universal Serial Bus (USB) USB function Firmware Receive IN token No Valid data in EP1 FIFO? Is there data to be transmitted to host? NAK Yes Yes Write 1 to EP1 FIFO empty enable (EP1EMPTYE in UIER1 = 1) Transmit data to host ACK Yes Space in EP1 FIFO? Set EP1 FIFO empty status (EP1EMPTY in UIFR1 = 1) EXIRQx No UIFR1/EP1EMPTY interrupt USB endpoint data register 1 (write one packet of data to UEDR1) Clear EP1 FIFO empty status (EP1EMPTY in UIFR1 = 0) Write 1 to EP1 packet enabl
Section 14 Universal Serial Bus (USB) 14.5.7 Bulk-Out Transfer (Dual FIFOs) (Endpoint 2) EP2 has two 64-byte FIFOs, but the user can receive data and read receive data without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the UIFR1/EP2READY bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately.
Section 14 Universal Serial Bus (USB) 14.5.8 Processing of USB Standard Commands and Class/Vendor Commands (1) Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing by the firmware. Whether or not command decoding is required by the firmware is indicated in table 14.5 below. Table 14.
Section 14 Universal Serial Bus (USB) 14.5.9 Stall Operations (1) Overview This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: Α. When the firmware forcibly stalls an endpoint for some reason Β. When a stall is performed automatically within the USB function module due to a USB specification violation. The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint.
Section 14 Universal Serial Bus (USB) (1) Transition from normal operation to stall USB function module (1-1) USB EPnSTL 0→1 Internal status bit 0 1. Set EPnSTL to 1 by firmware (1-2) Reference Transaction request EPnSTL 1 Internal status bit 0 1. Receive IN/OUT token from the host 2. Refer to EPnSTL To (1-3) (1-3) Stall Stall handshake EPnSTL 1 (SCME = 0) Internal status bit 0→1 To (2-1) or (3-1) 1. SCME is set to 0 2. EPnSTL is set to 1 3. Set internal status bit to 1 4.
Section 14 Universal Serial Bus (USB) (3) Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, when the information of this module differs from that returned to the host by the Get Descriptor, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the corresponding endpoint without regarding to EPnSTL, and returns a stall handshake (1-1 in figure 14.21).
Section 14 Universal Serial Bus (USB) 14.6 DMA Transfer Specifications Two methods of USB request and auto request are available for the DMA transfer of USB data. 14.6.1 DMAC Transfer by USB Request (1) Overview Only normal mode in full address mode (cycle steal mode) supports the transfer by a USB request of the on-chip DMAC. Endpoints that can be transferred by the on-chip DMAC are EP1 and EP2 in Bulk transfer (corresponding registers are UEDR1 and UEDR2).
Section 14 Universal Serial Bus (USB) Accordingly, this processing is automatically performed only when 64-byte data is sent. This processing is not performed automatically when data less than 64 bytes is sent. (b) EP1 DMA transfer procedure 1. Set the bits EP1T1 and EP1T0 in UDMAR. 2. Set DMAC (specifies the number of transfers in DMAC to transmit 150 bytes of data). 3. Activate DMAC. 4. Perform DMA transfer. 5. Write 1 to the EP1PKTE bit in UTRG0 by a DMA transfer end interrupt.
Section 14 Universal Serial Bus (USB) (b) EP2 DMA transfer procedure Perform DMAC transfer in 1 packet units. After setting the EP2READY flag, check the size of data received from the host and then set the data size as the number of DMAC transfers. 1. Set the bits EP2T1 and EP2T0 in UDMAR. 2. Wait for the EP2READY flag in UIFR1 to be set. 3. Set DMAC. Read the value in UESZ2 and specifies the size of received data (not more than 64 bytes) as the number of transfers. 4. Activate DMAC. 5.
Section 14 Universal Serial Bus (USB) (3) EP0, EP1, or EP3 DMA Transfer (a) EPnPKTE Bits of UTRG0 (n = 0i, 1, or 3) Note that 1 is not automatically written to EPnPKTE in case of auto-request transfer. Always write 1 to EPnPKTE by the CPU. The following example shows when 150-byte data is transmitted from EP1 to the host. In this case, 1 should be written to EP2PKTE three times as shown in figure 14.24. (b) EP1 DMA Transfer Procedure The DMAC transfer unit should be one packet.
Section 14 Universal Serial Bus (USB) (b) EP2 DMA Transfer Procedure The DMAC transfer unit should be one packet. Therefore, set the number of transfers so that it is equal to or less than the maximum packet size of each endpoint. 1. Wait for the UIFR1/EP2READY flag to be set. 2. DMAC settings for EP2 data transfer (such as auto-request and address setting). Read value of UESZ2 and specify number of transfers to match size of received data (64 bytes or less). 3.
Section 14 Universal Serial Bus (USB) 14.7 USB External Circuit Example Figures 14.26 and 14.27 show the USB external circuit examples of this LIS. USB Internal transceiver P36 VCC *3 DrVCC (3.3 V) VBUS (3.3 V) USD+ VCC (3.3 V) 1 Regulator * USD- 24 Ω DrVSS 24 Ω VSS UBPM 0: Bus-powered mode VCC *2 Pull-up control external circuit for full speed D+ 1.5 kΩ DGND VBUS (5 V) USB connector Notes: 1. Step-down to the operating voltage VCC (3.3 V) of this LSI. 2.
Section 14 Universal Serial Bus (USB) USB Internal transceiver VCC *2 *3 DrVCC P36 (3.3 V)IRQx VBUS (3.3 V) USD+ USD- DrVSS VSS UBPM VCC VCC 3.3V 24 Ω 24 Ω 1: Self-powered mode *1 VCC *1 1.5 kΩ Pull-up control external circuit for full speed VBUS D+ (5 V) D- GND USB connector Notes: 1. To protect the LSI, voltage applicable IC such as HD74LV-A series must be used even when the system power is turned off. 2.
Section 14 Universal Serial Bus (USB) 14.8 14.8.1 Usage Notes Emulator Usage Notes 1. If UEDR0o and UEDR2 are displayed using the I/O register window function, or the like, the EP0o FIFO or EP2 FIFO read pointer will not operate properly, preventing UEDR0o, UESZ0o, UEDR2, and UESZ2 from being read correctly. Therefore, UEDR0o and UEDR2 should not be displayed. 2.
Section 14 Universal Serial Bus (USB) 14.8.4 Setup Data Reception The following must be noted for the EP0s FIFO used to receive 8-byte setup data. The USB is designed to always receive setup commands. Accordingly, write from the UDC has higher priority than read from the LSI. If the reception of the next setup command starts while the LSI is reading data after completing reception, this data read from the LSI is forcibly cancelled and the next setup command write starts.
Section 14 Universal Serial Bus (USB) pointer that controls the internal module FIFO is updated and correct operation cannot be guaranteed. 14.8.8 Reset ⎯ The manual reset during USB communication operations must not be executed, since the LSI may stop with the state of USD+ and USD- pins maintained. This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilization time has passed.
Section 14 Universal Serial Bus (USB) 14.8.10 Level Shifter for VBUS and IRQx Pins The VBUS and IRQx pins of this USB module must be connected to the USB connector’s VBUS pin via a level shifter. This is because the USB module has a circuit that operates by detecting USB cable connection or disconnection. Even if the power of the device incorporating this USB module is turned off, 5-V power is applied to the USB connector’s VBUS pin while the USB cable is connected to the device set.
Section 14 Universal Serial Bus (USB) Procedure to enter power-down mode (1) Specify IRQ6 to falling edge sensitive (Set IRQ6E in IER to 1) (Write IRQ6SCB and IRQ6SCA in ISCRH to 01 (2) Detect USB bus suspend state USPND pin = High (3) IRQ6 = Low (falling edge output) Set IRQ6F in ISR to 1 Set SPRSi and SPRSs in UIFR3 to 1 (4) Confirm SPRSs in UIFR3 as 1 Clear IRQ6E in IER to 0* Clear SPRSi in UIFR3 to 0 (5) IRQ6 = High (6) Enter USB module stop 2 state (Stop MSTPB0 in MSTPCRB to 1) Procedure t
Section 14 Universal Serial Bus (USB) USB bus state (10) Resume → Normal (1) (2) Normal Suspend USPND (23) SOF (10) IRQ6 (3) (5) (11) ISR/IRQ6F (3) (4) (11) UIFR3/SPRSi (3) (4) (18) (19) UIFR3/SPRSs (3) (4) (18) (19) (20) (14) UIFR3/SOF USB module stop power-down mode (24) (15) (6) (8) (12) System clock (9) φ USB internal clock (13) (14) (9) (7) (16) UIFR3/ CK48READY (21) CLK48 (48MHz) (7) USB operating clock (48MHz) (7) (17) (22) Power-down mode 4 ms wait for osci
Section 14 Universal Serial Bus (USB) 14.8.14 Pin Processing when USB Not Used Pin processing should be performed as follows. DrVCC = VCC, DrVSS = 0 V, USD+ = USD− = USPND = open state, VBUS = UBPM = 0 V 14.8.15 Notes on TR Interrupt Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i, EP1, or EP3. The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host. However, at the timing shown in figure 14.
Section 14 Universal Serial Bus (USB) Rev.7.00 Dec.
Section 15 A/D Converter Section 15 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to six analog input channels to be selected. The block diagram of the A/D converter is shown in figure 15.1. 15.1 Features • 10-bit resolution • Six input channels • Conversion time: 8.1 µs per channel (at 16-MHz operation), 10.7 µs per channel (at 24-MHz operation), 21.
Section 15 A/D Converter Bus interface Module data bus VCC Successive approximation register 10 bit D/A Vref A D D R A A D D R B A D D R C A D D R D A D C S R Internal data bus A D C R + AN0 AN2 AN3 AN14 φ/2 Multiplexer AN1 AN15 Comparator φ/4 Control circuit φ/8 φ/16 Sample and hold circuit ADI interrupt signal ADTRG Time conversion start trigger from TPU Off during A/D conversion standby On during A/D conversion VSS Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control r
Section 15 A/D Converter 15.2 Input/Output Pins Table 15.1 summarizes the input pins used by the A/D converter. The AN0 to AN3 and AN14 to AN15 pins are analog input pins. The VCC and VSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the reference voltage pin for the A/D conversion. Table 15.
Section 15 A/D Converter 15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide.
Section 15 A/D Converter Bit Bit Name Initial Value R/W Description 6 ADIE R/W A/D Interrupt Enable 0 A/D conversion end interrupt (ADI) request enabled when 1 is set. 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. It can be set to 1 by software, the timer conversion start trigger, and the A/D external trigger (ADTRG).
Section 15 A/D Converter 15.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W Enables the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0).
Section 15 A/D Converter 15.4 Interface to Bus Master ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus master accesses to the upper byte of the registers directly while to the lower byte of the registers via the temporary register (TEMP). Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data will be transferred to the CPU and the lower-byte data will be transferred to TEMP.
Section 15 A/D Converter 15.5 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 15.5.
Section 15 A/D Converter 15.5.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH3 and CH2 = 00, AN4 when CH3 and CH2 = 01, or AN8 when CH3 and CH2 = 10). 2.
Section 15 A/D Converter 15.5.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Tables 15.3 and 15.4 show the A/D conversion time. As indicated in figure 15.5, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Section 15 A/D Converter Table 15.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 CKS1 = 1 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start delay tD 18 — 33 10 — 17 6 — 9 4 — 5 Input sampling time tSPL — 127 — — 63 — — 31 — — 15 — A/D conversion time tCONV 515 — 530 259 — 266 131 — 134 67 — 68 Note: All values represent the number of states. Table 15.
Section 15 A/D Converter 15.6 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DMAC can be activated by an ADI interrupt. Table 15.5 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag DMAC Activation ADI A/D conversion completed ADF 15.
Section 15 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.7 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.8 A/D Conversion Precision Definitions (2) Rev.7.00 Dec.
Section 15 A/D Converter 15.8 Usage Notes 15.8.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 20, Power-Down Modes. 15.8.
Section 15 A/D Converter 15.8.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range VSS ≤ ANn ≤ Vref. • Vref input range The analog reference voltage input at the Vref pin set is the range Vref ≤ Vcc. 15.8.
Section 15 A/D Converter Rev.7.00 Dec.
Section 16 RAM Section 16 RAM The HD64F2218, HD64F2218U, and HD64F2218CU have 12 kbytes of on-chip high-speed static RAM. The HD6432217, HD64F2211, HD64F2211U, and HD64F2211CU have 8 kbytes of onchip high-speed static RAM. The HD6432210 and HD6432210S have 4 kbytes of on-chip highspeed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
Section 16 RAM Rev.7.00 Dec.
Section 17 Flash Memory (F-ZTAT Version) Section 17 Flash Memory (F-ZTAT Version) The features of the on-chip flash memory are summarized below. The block diagram of the flash memory is shown in figure 17.1. 17.
Section 17 Flash Memory (F-ZTAT Version) • Automatic bit rate adjustment ⎯ With data transfer in SCI boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. • Programming/erasing protection ⎯ Sets hardware protection, software protection, and error protection against flash memory programming/erasing. • Programmer mode ⎯ Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode.
Section 17 Flash Memory (F-ZTAT Version) 17.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 17.2. In user mode, flash memory can be read but not programmed or erased. The boot and user program modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 17.1.
Section 17 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI or USB communication.
Section 17 Flash Memory (F-ZTAT Version) 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 17 Flash Memory (F-ZTAT Version) 17.3 Block Configuration Figure 17.5 shows the block configuration of 128-kbyte flash memory in the HD64F2218, HD64F2218U, HD64F2218CU, HD64F2212, HD64F2212U and HD64F2212CU. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into one kbyte (four blocks), 28 kbytes (one block), 16 kbytes (one block), eight kbytes (two blocks), and 32 kbytes (two blocks).
Section 17 Flash Memory (F-ZTAT Version) Figure 17.6 shows the block configuration of 64-kbyte flash memory in the HD64F2217CU, HD64F2211, HD64F2211U and HD64F2211CU. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into one kbyte (four blocks), 28 kbytes (one block), and 16 kbytes (one block), eight kbytes (two blocks). Erasing is performed in these divided units.
Section 17 Flash Memory (F-ZTAT Version) Figure 17.7 shows the block configuration of the 32 Kbyte flash memory in the HD64F2210CU. The thick lines indicate erase blocks, the narrow lines indicate programming units, and the values in the boxes are addresses. The flash memory is divided into units one Kbyte (four blocks) or 28 Kbytes (one block) in size, and erasing is performed in these units. Programming is performed in 128-byte units starting from an address whose lower eight bits are H'00 or H'80.
Section 17 Flash Memory (F-ZTAT Version) 17.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 17.2. Table 17.
Section 17 Flash Memory (F-ZTAT Version) 17.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 17.8, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W 7 FWE R —* Description Flash Write Enable Reflects the input level at the FWE pin.
Section 17 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 PV1 R/W Program-Verify 0 When this bit is set to 1, the flash memory transits to program-verify mode. When it is cleared to 0, programverify mode is cancelled. [Setting condition] When FWE = 1 and SWE1 = 1 1 E1 0 R/W Erase When this bit is set to 1 while the SWE1 and ESU1 bits are 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled.
Section 17 Flash Memory (F-ZTAT Version) 17.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) are to be erased.
Section 17 Flash Memory (F-ZTAT Version) 17.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified.
Section 17 Flash Memory (F-ZTAT Version) 17.5.6 Serial Control Register X (SCRX) SCRX performs register access control. Bit Bit Name Initial Value 7 to 4 — All 0 R/W Description R/W Reserved The write value should always be 0. 3 FLSHE 0 R/W Flash Memory Control Register Enable: Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers.
Section 17 Flash Memory (F-ZTAT Version) 17.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17.3.
Section 17 Flash Memory (F-ZTAT Version) 0 1 01× EMLE This LSI FWE MD2 to MD0* Flash memory Host Write data reception Verify data transmission RxD2 SCI_2 TxD2 On-chip RAM Legend: × : Don’t care Note: * Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 200ns) with respect to the reset release timing. Figure 17.8 System Configuration in SCI Boot Mode Table 17.4 shows the boot mode operations between reset end and branching to the programming control program. 1.
Section 17 Flash Memory (F-ZTAT Version) 5. In boot mode, a part of the on-chip RAM area (four kbytes) is used by the boot program. The area to which the programming control program is transferred from the host is 8 kbytes (H'FFC000 to H'FFDFFF) in the HD64F2218 and HD64F2212 and 4 kbytes (H'FFD000 to H'FFDFFF) in the HD64F2211. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6.
Section 17 Flash Memory (F-ZTAT Version) Table 17.
Section 17 Flash Memory (F-ZTAT Version) 17.6.2 USB Boot Mode (HD64F2218U, HD64F2212U, and HD64F2211U) • Features ⎯ Selection of bus-powered mode or self-powered mode ⎯ Supports the USB operating clock generation by 16 MHz system clock with PLL3 multiplication (FWE = 1, MD2 to MD0 = 011) or 24 MHz system clock with PLL2 multiplication (FWE = 1, MD2 to MD0 = 010) ⎯ D+ pull up control connection supported for P36 pin only ⎯ See table 17.6 for enumeration information Table 17.
Section 17 Flash Memory (F-ZTAT Version) • Overview When a reset start preformed after the pins of this LSI have been set to boot mode, a boot program incorporated in the microcomputer beforehand is activated, and the prepared programming control program is transmitted sequentially to the host using the USB. With this LSI, the programming control program received by the USB is written to a programming control program area in on-chip RAM.
Section 17 Flash Memory (F-ZTAT Version) 3. Set the frequency for transmission from the host as a numeric value in units of MHz × 100 (ex: 16.00 MHz → H'0640, 24.00 MHz → H'0960). 4. In boot mode, the 4-kbyte on-chip RAM area H'FFE000 to H'FFEFBF is used by the boot program.
Section 17 Flash Memory (F-ZTAT Version) Table 17.
Section 17 Flash Memory (F-ZTAT Version) Item Host Operation Operation of this LSI Transfer of programming control program and sum value Transmits programming control program in N-byte divisions.
Section 17 Flash Memory (F-ZTAT Version) 17.6.3 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Section 17 Flash Memory (F-ZTAT Version) 17.7 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 17.11 shows an example of emulation of real-time flash memory programming. 1.
Section 17 Flash Memory (F-ZTAT Version) An example in which flash memory block area EB0 is overlapped is shown in Figure 17.12. 1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range of H'FFD000 to H'FFD3FF. 2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area among one of the EB0 to EB3 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4.
Section 17 Flash Memory (F-ZTAT Version) 17.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Section 17 Flash Memory (F-ZTAT Version) Write pulse application subroutine Start of programming Subroutine Write Pulse START Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 17 Flash Memory (F-ZTAT Version) 17.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in Figure 17.14 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1, 2 (EBR1, EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E1 bit is set to 1 is the flash memory erase time. 4.
Section 17 Flash Memory (F-ZTAT Version) *1 Start Set SWE1 bit in FLMCR1 *2 Wait (x) μs n=1 *4 Set EBR1 (2) Enable WDT Set ESU1 bit in FLMCR1 *2 Wait (y) μs Set E1 bit in FLMCR1 Start erasing *2 Wait (z) μs Clear E1 bit in FLMCR1 Halt erasing *2 Wait (α) μs Clear ESU1 bit in FLMCR1 *2 Wait (β) μs Disable WDT Set EV1 bit in FLMCR1 Wait (γ) μs *2 Set block start address as verify address H'FF dummy write to verify address Wait (ε) μs *2 Read verify data *3 Verify data = all 1s? Increment
Section 17 Flash Memory (F-ZTAT Version) 17.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode.
Section 17 Flash Memory (F-ZTAT Version) The FLMCR1, FLMCR2, EBR1 and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. 17.
Section 17 Flash Memory (F-ZTAT Version) 17.11 Programmer Mode In programmer mode, a PROM programmer can perform programming/erasing via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas Technology 128-kbyte or 64-kbyte flash memory on-chip MCU device type. Memory map in programmer mode is shown in Figure 17.15.
Section 17 Flash Memory (F-ZTAT Version) 17.12 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to. • Standby mode All flash memory circuits are halted. • Power-down state The flash memory can be read when part of the power supply circuit is halted and the LSI operates by subclocks. Table 17.
Section 17 Flash Memory (F-ZTAT Version) 17.13 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. • Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with on-chip flash memory (FZTAT128V3A, FZTAT64V3A).
Section 17 Flash Memory (F-ZTAT Version) • Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. • Do not set or clear the SWE1 bit during execution of a program in flash memory.
Section 17 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing possible Wait time: θ φ min 0 μs tOSC1 VCC tMDS*3 FWE min 0 μs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Section 17 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing Wait time: θ possible φ min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
*4 *4 Programming/ erasing possible Wait time: x Wait time: x Programming/ erasing possible Wait time: x Programming/ erasing possible Programming/ erasing possible Wait time: x Section 17 Flash Memory (F-ZTAT Version) *4 *4 φ tOSC1 VCC min 0μs FWE 2 tMDS* tMDS MD2 to MD0 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setti
Section 17 Flash Memory (F-ZTAT Version) 17.14 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 17.9 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 17.9 is read in the masked ROM version, an undefined value will be returned.
Section 18 Masked ROM Section 18 Masked ROM This LSI incorporates a masked ROM which has the following features. 18.1 Features • Size Product Class ROM Size ROM Address (Modes 6 and 7) H8S/2218 Group HD6432217 64 kbytes H'000000 to H'00FFFF H8S/2212 Group HD6432211 64 kbytes H'000000 to H'00FFFF HD6432210, HD6432210S 32 kbytes H'000000 to H'007FFF • Connected to the bus master through 16-bit data bus, enabling one-state access to both byte data and word data. Figure 18.
Section 18 Masked ROM Rev.7.00 Dec.
Section 19 Clock Pulse Generator Section 19 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of a main clock oscillator, duty adjustment circuit, clock select circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, waveform shaping circuit, PLL (Phase Locked Loop) circuit, and USB operating clock selection circuit.
Section 19 Clock Pulse Generator 19.1 Register Descriptions The on-chip clock pulse generator has the following registers. • System clock control register (SCKCR) • Low-power control register (LPWRCR) 19.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and medium-speed mode. Bit Bit Name Initial Value R/W Description 7 PSTOP φ Clock Output Disable 0 R/W Controls φ output. The operation of this bit changes depending on the operating mode. For details, see section 20.
Section 19 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2 SCK2 0 R/W System Clock Select 2 to 0 1 SCK1 0 R/W 0 SCK0 0 R/W These bits select the bus master clock. To operate in subactive mode or watch mode, clear the SCK2 to SCK0 bits to 0. 000: High-speed mode 001: Medium-speed clock is φ/2 010: Medium-speed clock is φ/4 011: Medium-speed clock is φ/8 100: Medium-speed clock is φ/16 101: Medium-speed clock is φ/32 11×: Setting prohibited Legend: ×: Don’t care 19.1.
Section 19 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 6 LSON Low Speed ON Flag 0 R/W 0: When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to watch mode* or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled.
Section 19 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 3 RFCUT 0 R/W Built-in Feedback Resistor Control Selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input. This bit should not be accessed when a crystal oscillator is used. After this bit is set when using external clock input, a transition should initially be made to software standby mode.
Section 19 Clock Pulse Generator 19.2 System Clock Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 19.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 19.2. Select the damping resistance Rd according to table 19.1. An AT-cut parallel-resonance crystal should be used.
Section 19 Clock Pulse Generator 19.2.2 Inputting External Clock An external clock signal can be input as shown in an example in figure 19.4. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. When complementary clock input to XTAL pin, the external clock input should be fixed high in standby mode, subactive mode, subsleep mode, or watch mode.
Section 19 Clock Pulse Generator Table 19.4 External Clock Input Conditions when Duty Adjustment Circuit Is not Used Test Item Symbol min max Min max min max Unit Conditions External clock input low pulse width tEXL 80 — 31.25 — 20.8 — ns Figure 19.5 External clock input high pulse width tEXH 80 — 31.25 — 20.8 — ns External clock rise time tEXr — 15 — 6.25 — 5.25 ns External clock fall time tEXf — 15 — 6.25 — 5.25 ns tEXH tEXL VCC × 0.
Section 19 Clock Pulse Generator 19.6 Subclock Oscillator 19.6.1 Connecting 32.768-kHz Crystal Resonator supply a clock to the subclock divider, connect a 32.768-kHz crystal resonator, as shown in figure 19.6. Figure 19.7 shows the equivalence circuit for a 32.768-kHz oscillator. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ.) Note: C1 and C2 are reference values including the floating capacitance of the board. Figure 19.6 Example Connection of 32.768-kHz Quartz Oscillator Ls Cs Rs OSC1 OSC2 Co Co = 1.
Section 19 Clock Pulse Generator 19.7 Subclock Waveform Generation Circuit To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 19.1.2, Low Power Control Register (LPWRCR). No sampling is performed in subactive mode, subsleep mode, or watch mode. 19.
Section 19 Clock Pulse Generator 19.9 Usage Notes 19.9.1 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide.
Section 19 Clock Pulse Generator This LSI Request switchover of external clock Interrupted external signal Control cycle External clock 1 External clock 2 Selector External clock switchover signal Ouptut port External interrupt EXTAL Figure 19.
Section 20 Power-Down Modes Section 20 Power-Down Modes In addition to the normal program execution state, this LSI has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. This LSI's operating modes are high-speed mode and five power down modes: 1. 2. 3. 4. 5. 6. 7. 8.
Section 20 Power-Down Modes Table 20.
Section 20 Power-Down Modes Reset execution state Program-halted state STBY pin = Low Manual reset state Power-on reset state MRES pin = High Hardware standby mode STBY pin = High RES pin = Low RES pin = High SSBY = 0, LSON = 0 Program execution state Sleep mode (main clock) SLEEP instruction High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP Instruction SLEEP Instruction SSBY = 1, PSS = 1, SSBY = 1, PSS = 1, DTON = 1, LSON = 0 DTON = 1, LSON =
Section 20 Power-Down Modes Table 20.
Section 20 Power-Down Modes 20.1 Register Descriptions The registers relating to the power down mode are shown below. For details on the low power control register (LPWRCR), refer to section 19.1.2, Low Power Control Register (LPWRCR). For details on the system clock control register (SCKCR), refer to section 19.1.1, System Clock Control Register (SCKCR).
Section 20 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits select the MCU wait time for clock stabilization when cancel software standby mode, watch mode, or subactive mode by an external interrupt. With a crystal oscillator (tables 20.3 and 20.4), select a wait time of tOSC2 ms (oscillation stabilization time) or more, depending on the operating frequency.
Section 20 Power-Down Modes 20.1.2 Timer Control/Status Register (TCSR_1) TCSR_1 controls the operation in power-down mode transition. Bit Bit Name 7 to 5 ⎯ Initial Value R/W All 0 ⎯ Description Reserved The write value should always be 0. 4 PSS 0 R/W Prescaler Select 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode or software standby mode.
Section 20 Power-Down Modes 20.1.3 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. Setting a bit to 1, causes the corresponding module to enter module stop mode, while clearing the bit to 0 clears the module stop mode.
Section 20 Power-Down Modes MSTPCRC Bit Bit Name Initial Value R/W Module 7 MSTPC7* 1 R/W ⎯ 6 MSTPC6* 1 R/W ⎯ 5 MSTPC5* 1 R/W ⎯ 4 MSTPC4* 1 R/W ⎯ 3 MSTPC3* 1 R/W ⎯ 2 MSTPC2* 1 R/W ⎯ 1 MSTPC1 0 R/W Flash Memory (This bit is reserved in the masked ROM version; setting is disabled.) Note: Setting of the flash memory module stop mode should be carried out while the programs in the on-chip RAM and external memory are executed.
Section 20 Power-Down Modes Program executed module Execute flash memory program Power-down mode setting required? No Flash memory Yes For interrupt processing, enable RAM emulation function of EB0 area in flash memory and copy part of vector address and program to on-chip RAM Branch to on-chip RAM program Write 1 to flash memory module stop bit using on-chip RAM program Operation in power-down mode by entering flash memory module stop mode Flash memory program execution is required? No On-chip RA
Section 20 Power-Down Modes 20.1.4 Extended Module Stop Register (EXMDLSTP) EXMDLSTP controls the clock supply of the RTC and USB, performs module stop mode control. Setting a bit to 1, causes the corresponding module to enter module stop mode, while clearing the bit to 0 clears the module stop mode. Bit Bit Name Initial Value R/W 7 to 2 ⎯ Undefined ⎯ 1 RTCSTOP 0 R/W RTC 0 USBSTOP1 0 R/W USB 20.2 Module Reserved Read is undefined. These bits should not to be modified.
Section 20 Power-Down Modes Figure 20.3 shows the timing for transition to and clearance of medium-speed mode. Note: * Supported only by the H8S/2218 Group. Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 20.3 Medium-Speed Mode Transition and Clearance Timing 20.3 Sleep Mode 20.3.
Section 20 Power-Down Modes 20.4 Software Standby Mode 20.4.1 Transition to Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the PSS bit in TCSR_1 are cleared to 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
Section 20 Power-Down Modes 20.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. • Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least tOSC2 ms (the oscillation stabilization time). Table 20.3 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. • Using an External Clock Set bits STS2 to STS0 as any value.
Section 20 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) SLEEP instruction NMI exception handling Oscillation stabilization time tOSC2 Figure 20.4 Software Standby Mode Application Example 20.5 Hardware Standby Mode 20.5.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
Section 20 Power-Down Modes 20.5.3 Hardware Standby Mode Timing Figure 20.5 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time tOSC1 Reset exception handling Figure 20.
Section 20 Power-Down Modes Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t ≥100 ns tOSC RES tNMIRH NMI Figure 20.7 Timing of Recovery from Hardware Standby Mode 20.6 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules.
Section 20 Power-Down Modes 20.7 Watch Mode 20.7.1 Transition to Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR_1 PSS = 1. In watch mode, the CPU is stopped and peripheral modules other than RTC are also stopped.
Section 20 Power-Down Modes 20.8 Subsleep Mode 20.8.1 Transition to Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR_1 PSS bit = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped. Peripheral modules other WDT and RTC are also stopped. The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding the A/D converter) and I/O ports are retained.
Section 20 Power-Down Modes 20.9 Subactive Mode 20.9.1 Transition to Subactive Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR_1 PSS bit = 1, CPU operation shifts to subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is made to subactive mode.
Section 20 Power-Down Modes 20.10 Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and subactive modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. 20.10.
Section 20 Power-Down Modes 20.12 Usage Notes 20.12.1 I/O Port Status In software standby mode or watch mode, I/O port states are retained. In addition, if the OPE bit is set to 1, the address bus and bus control signal output are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 20.12.
Section 20 Power-Down Modes 20.12.6 Entering Subactive/Watch Mode and DMAC and DTC Module Stop To enter subactive or watch mode, set DMAC to module stop (write 1 to the MSTPA7 bit) and reading the MSTPA7 bit as 1 before transiting mode. After transiting from subactive mode to active mode, clear module stop. When a DMAC activation source is generated in subactive mode, the DMAC is activated when module stop is cleared following the transition to active mode. 20.12.
Section 20 Power-Down Modes Rev.7.00 Dec.
Section 21 List of Registers Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • Register Addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The access size is indicated. 2.
Section 21 List of Registers 21.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module USB USB endpoint receive data size register 0o UESZ0o 8 H'C000BC 8 3 USB endpoint receive data size register 2 UESZ2 8 H'C000BD 8 3 USB interrupt flag register 0 UIFR0 8 H'C000C0 8 3 USB interrupt flag register 1 UIFR1 8 H'C000C1 8 3 USB interrupt flag register 3 UIFR3 8 H'C000C3 8 3 USB interrupt enable register 0 UIER0 8 H'C000C4 8 3 USB inte
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module SYSTEM Standby control register SBYCR 8 H’FDE4 8 2 System control register SYSCR 8 H’FDE5 8 2 System clock control register SCKCR 8 H’FDE6 8 2 Mode control register MDCR 8 H’FDE7 8 2 Module stop control register A MSTPCRA 8 H’FDE8 8 2 Module stop control register B MSTPCRB 8 H’FDE9 8 2 Module stop control register C MSTPCRC 8 H’FDEA 8 2
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module TPU Timer start register TSTR 8 H'FEB0 16 2 Timer synchro register TSYR 8 H'FEB1 16 2 Interrupt priority register A IPRA 8 H'FEC0 8 2 Interrupt priority register B IPRB 8 H'FEC1 8 2 Interrupt priority register C IPRC 8 H'FEC2 8 2 Interrupt priority register D IPRD 8 H'FEC3 8 2 Interrupt priority register E IPRE 8 H'FEC4 8 2 Interrupt pri
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module DMAC I/O address register 1B IOAR1B 16 H'FEFC 16 2 Transfer count register 1B ETCR1B 16 H'FEFE 16 2 Port 1 data register P1DR 8 H'FF00 8 2 Port 3 data register P3DR 8 H'FF02 8 2 Port 7 data register P7DR 8 H'FF06 8 2 Port A data register PADR 8 H'FF09 8 2 Port B data register PBDR 8 H'FF0A 8 2 Port C data register PCDR 8 H'FF0B 8 2
Section 21 List of Registers Number Data Bus of Access Width States Module TPU_2 Register Name Abbreviation Number of Bits Address Timer control register_2 TCR_2 8 H'FF30 16 2 Timer mode register_2 TMDR_2 8 H'FF31 16 2 Timer I/O control register 2 TIOR_2 8 H'FF32 16 2 Timer interrupt enable register 2 TIER_2 8 H'FF34 16 2 Timer status register_2 TSR_2 8 H'FF35 16 2 Timer counter_2 TCNT_2 16 H'FF36 16 2 Timer general register A_2 TGRA_2 16 H'FF38 16 2 Timer gene
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module SCI_0 Serial mode register_0 SMR_0 8 H'FF78 8 2 Bit rate register_0 BRR_0 8 H'FF79 8 2 Serial control register_0 SCR_0 8 H'FF7A 8 2 Transmit data register_0 TDR_0 8 H'FF7B 8 2 Serial status register_0 SSR_0 8 H'FF7C 8 2 Receive data register_0 RDR_0 8 H'FF7D 8 2 Smart card mode register_0 SCMR_0 8 H'FF7E 8 2 Serial mode register_2 SMR_2
Section 21 List of Registers Register Name Abbreviation Number of Bits Address Number Data Bus of Access Width States Module PORT Port 1 register PORT1 8 H'FFB0 8 2 Port 3 register PORT3 8 H'FFB2 8 2 Port 4 register PORT4 8 H'FFB3 8 2 Port 7 register PORT7 8 H'FFB6 8 2 Port 9 register PORT9 8 H'FFB8 8 2 Port A register PORTA 8 H'FFB9 8 2 Port B register PORTB 8 H'FFBA 8 2 Port C register PORTC 8 H'FFBB 8 2 Port D register PORTD 8 H'FFBC 8 2 Port E
Section 21 List of Registers 21.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as two lines and 32-bit registers as four lines.
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module UISR1 ⎯ ⎯ ⎯ ⎯ ⎯ EP2 READYS EP1TRS EP1 EMPTYS USB UISR3 CK48 READYS SOFS SETCS ⎯ ⎯ ⎯ ⎯ VBUSiS UDSR ⎯ ⎯ ⎯ ⎯ ⎯ EP1DE EP3DE EP0iDE UCVR ⎯ ⎯ CNFV0 ⎯ ⎯ ⎯ ⎯ ⎯ UTSTR0 PTSTE ⎯ ⎯ ⎯ SUSPEND OE FSE0 VPO UTSTR1 VBUS UBPM ⎯ ⎯ ⎯ RCV VP VM UTSTR2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ UTSTRB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ UTSTRC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ UTSTRD ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT P3DDR ⎯ P36DDR ⎯ ⎯ ⎯ P32DDR P31DDR P30DDR P7DDR P77DDR P76DDR P75DDR P74DDR ⎯ ⎯ P71DDR P70DDR PADDR ⎯ ⎯ ⎯ ⎯ PA3DDR PA2DDR PA1DDR PA0DDR PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PDDDR PD7DDR PD6DDR
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 BSC ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 WCRH W71 W70 W61 W60 W51 W50 W41 W40 WCRL W31 W30 W21 W20 W11 W10 W01 W00 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 BCRL BRLE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ WAITE RAMER ⎯ ⎯ ⎯ ⎯ RAMS ⎯ RAM1 RAM0 FLASH MAR0A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC Bit 23 Bit
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR1B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRC_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRD_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCR_1 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IO
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RSECDR BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 RTC RMINDR BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00 RHRDR BSY ⎯ HR11 HR10 HR03 HR02 HR01 HR00 RWKDR BSY ⎯ ⎯ ⎯ ⎯ WK2 WK1 KWK0 RTCCR1 RUN 12/24 PM RST ⎯ ⎯ ⎯ ⎯ RTCCR2 ⎯ ⎯ FOIE WKIE DYIE HRIE MNIE SEIE ⎯ RCS6 RCS5 ⎯ RCS3 RCS2 RCS1 RCS0 DMACR0A* 1 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMAC
Section 21 List of Registers Register Name SMR_2 SMR_2* 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_2 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 BRR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCR_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE RDRF ORER FER PER TEND MPB MPBT TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_2 Bit 7 Bit 6 Bit 5 Bit 4
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT PORT3 ⎯ P36 ⎯ ⎯ ⎯ P32 P31 P30 PORT4 ⎯ ⎯ ⎯ ⎯ P43 P42 P41 P40 PORT7 P77 P76 P75 P74 ⎯ ⎯ P71 P70 PORT9 P97 P96 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTA ⎯ ⎯ ⎯ ⎯ PA3 PA2 PA1 PA0 PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6
Section 21 List of Registers 21.
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Module Stop Watch Subactive Subsleep Standby Standby Module UTSTR0 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized USB UTSTR1 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UTSTR2 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UTSTRB Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UTSTRC Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initializ
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Module Stop Watch Subactive Subsleep Standby Standby Module PDDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT PEDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PGDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PAPCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PBPCR
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Module Stop Watch Subactive Subsleep Standby Standby Module MAR0A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC IOAR0A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ETCR0A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MAR0B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IOAR0B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ETCR0B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MAR1A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IOAR1A ⎯ ⎯ ⎯ ⎯ ⎯
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module TCR_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_1 TMDR_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_1 Initialized Initiali
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Module Stop Watch Subactive Subsleep Standby Standby Module SMR_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_0 BRR_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_0 Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized
Section 21 List of Registers Register Power-on Manual High- Medium- Software Hardware Name Reset Reset Speed Speed Sleep Module Stop Watch Subactive Subsleep Standby Standby Module PORT1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT PORT3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT9 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 21 List of Registers Rev.7.00 Dec.
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, PLLVCC, DrVCC –0.3 to +4.3 V Input voltage Vin –0.3 to VCC +0.3 V Reference voltage Vref –0.3 to VCC +0.3 V Analog input voltage VAN –0.3 to VCC +0.
Section 22 Electrical Characteristics 22.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 22.1. (1) Mask ROM versions (except for HD6432210S) Frequency f System clock 24 MHz 16 MHz 6 MHz Sub clock 32.768 kHz 0 2.4 2.7 3.6 3.0 Power ssupply voltage Vcc, PLLVcc, DrVcc (V) (2) Masked ROM version (HD6432210S) Frequency f System clock 24 MHz 16 MHz 6 MHz Condition A: Vcc = PLLVcc = DrVcc = 2.4 to 3.6V Vref = 2.
Section 22 Electrical Characteristics 22.3 DC Characteristics Table 22.2 lists the DC characteristics. Table 22.3 lists the permissible output currents. Table 22.2 DC Characteristics Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.
Section 22 Electrical Characteristics Item Test Conditions Min. Typ. Max. Unit RES, STBY, VIL MD2 to MD0, TRST, TCK, TMS, TDI, EMLE, VBUS, 4 UBPM, FWE* –0.3 — VCC × 0.1 V EXTAL, NMI, ports 1, 3, 4, 7, 9, and A to G –0.3 — VCC × 0.2 V Output high voltage All output pins VOH VCC – 0.5 — — V IOH = –200 µA VCC – 1.0 — — V IOH = –1 mA Output low voltage All output pins VOL — — 0.4 V IOL = 0.
Section 22 Electrical Characteristics Item Current dissipation*1 Min. Typ. ICC*2 — 45 mA 30 VCC = 3.3 V VCC = 3.6 V (USB operates) f = 16 MHz, When PLL3 is used — 41 60 mA VCC = 3.3 V VCC = 3.6 V f = 24 MHz, When PLL2 is used Sleep mode — 16 30 mA VCC = 3.3 V VCC = 3.6 V f = 16 MHz, When USB and PLL are halted — 22 45 mA VCC = 3.3 V VCC = 3.6 V f = 24 MHz, When USB and PLL are halted All modules other than flash memory stopped — 16 — VCC = 3.
Section 22 Electrical Characteristics 1. Current dissipation values are for VIH min. = VCC – 0.2 V and VIL max. = 0.2 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 2. ICC depends on VCC and f as follows (Reference): ICC max. = 5 (mA) + 0.52 (mA/(MHz x V)) × VCC × f (normal operation, USB halted) ICC max. = 9 (mA) + 0.60 (mA/(MHz x V)) × VCC × f (normal operation, USB operated) ICC max. = 1 (mA) + 0.51 (mA/(MHz x V)) × VCC × f (sleep mode) 3.
Section 22 Electrical Characteristics 22.4 AC Characteristics Figure 22.2 shows, the test conditions for the AC characteristics. 3V RL LSI output pin C RH C=30 pF RL= 2.4 kΩ RH=12 kΩ Input/output timing measurement levels • Low level : 1.3 V (2.4 V ≤ Vcc < 2.7 V) : 0.8 V (2.7 V ≤ Vcc ≤ 3.6 V) • High level : 1.3 V (2.4 V ≤ Vcc < 2.7 V) : 2.0 V (2.7 V ≤ Vcc ≤ 3.6 V) Figure 22.2 Output Load Circuit Rev.7.00 Dec.
Section 22 Electrical Characteristics 22.4.1 Clock Timing Table 22.4 lists the clock timing Table 22.4 Clock Timing Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.
Section 22 Electrical Characteristics Condition A Condition B Condition C Condition D Item Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Test Conditions Figure 22.4 External clock output tDEXT stabilization delay time 1000 — 500 — 500 — 500 — µs Subclock stabilization time tOSC3 — — 2 — 2 — 2 s Subclock oscillator frequency fSUB 32.768 32.768 32.768 32.768 Subclock (φSUB) cycle time fSUB 30.5 30.5 30.5 30.5 4 kHz µs tcyc tCH tCf φ tCL tCr Figure 22.
Section 22 Electrical Characteristics 22.4.2 Control Signal Timing Table 22.5 lists the control signal timing. Table 22.5 Control Signal Timing Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.
Section 22 Electrical Characteristics φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 22.5 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 22.6 Interrupt Input Timing Rev.7.00 Dec.
Section 22 Electrical Characteristics 22.4.3 Bus Timing Table 22.6 shows, Bus Timing. Table 22.6 Bus Timing Condition A: VCC = PLL VCC =Dr VCC =2.4 V to 3.6 V, Vref=2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC =Dr VCC =2.7 V to 3.6 V, Vref=2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.
Section 22 Electrical Characteristics Condition A Condition B Symbol Min. Max. Read data access time 3 tACC3 — 2.0 × tcyc — – 90 2.0 × tcyc — – 65 2.0 × tcyc ns – 40 Figures 22.7, 22.10 Read data access time 4 tACC4 — 2.5 × tcyc — – 90 2.5 × tcyc — – 65 2.5 × tcyc ns – 35 Figure 22.8 Read data access time 5 tACC5 — 3.0 × tcyc — – 90 3.0 × tcyc — – 65 3.0 × tcyc ns – 40 WR delay time 1 tWRD1 — 90 — 50 — 20 ns Figure 22.
Section 22 Electrical Characteristics T1 T2 φ tAD A23 to A0 tCSD tAH tAS CS5 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWSW1 tWDD tWDH D15 to D0 (write) Figure 22.7 Basic Bus Timing (Two-State Access) Rev.7.00 Dec.
Section 22 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0 tAS tAH tCSD CS5 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 22.8 Basic Bus Timing (Three-State Access) Rev.7.00 Dec.
Section 22 Electrical Characteristics T1 T2 TW T3 φ A23 to A0 CS5 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 22.9 Basic Bus Timing (Three-State Access with One Wait State) Rev.7.00 Dec.
Section 22 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 22.10 Burst ROM Access Timing (Two-State Access) Rev.7.00 Dec.
Section 22 Electrical Characteristics φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD A23 to A0, CS5 to CS0, AS, RD, HWR, LWR Figure 22.11 External Bus Release Timing Rev.7.00 Dec.
Section 22 Electrical Characteristics 22.4.4 Timing of On-Chip Supporting Modules Table 22.7 lists the timing of on-chip supporting modules. Table 22.7 Timing of On-Chip Supporting Modules Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.
Section 22 Electrical Characteristics Condition A Condition B Item SCI Symbol Min. Input clock cycle Condition C,D Max. Min. Max. Min. Max. Unit Asynchro- tScyc nous 4 — 4 — 4 — Synchronous 6 — 6 — 6 — tcyc Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 — 1.5 — 1.5 tcyc Input clock fall time tSCKf — 1.5 — 1.5 — 1.
Section 22 Electrical Characteristics T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 22.12 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 22.13 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22.14 TPU Clock Input Timing Rev.7.00 Dec.
Section 22 Electrical Characteristics tSCKW tSCKr tSCKf SCK0, SCK2 tScyc Figure 22.15 SCK Clock Input Timing SCK0, SCK2 tTXD TxD0, TxD2 (transmit data) tRXS tRXH RxD0, RxD2 (receive data) Figure 22.16 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 22.17 A/D Converter External Trigger Input Timing tTcyc tTCKH tTCKL TCK Figure 22.18 Boundary Scan TCK Input Timing TCK tTRSS tTRSS TRST tTRSW Figure 22.19 Boundary Scan TRST Input Timing (At Reset Hold) Rev.7.00 Dec.
Section 22 Electrical Characteristics TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD tTDOD TDO Figure 22.20 Boundary Scan Data Transmission Timing Rev.7.00 Dec.
Section 22 Electrical Characteristics 22.5 USB Characteristics Table 22.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 22.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used Conditions: VCC = PLL VCC = Dr VCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = 0 V, f = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit 2.
Section 22 Electrical Characteristics Rise Time USD+, USD- Fall Time 90% VCRS 90% 10% Differential Date Lines 10% tR tF Figure 22.21 Data Signal Timing USD+ Rs = 24 Ω Test Point CL = 50 pF USD- Rs = 24 Ω Test Point CL = 50 pF Figure 22.22 Test Load Circuit Rev.7.00 Dec.
Section 22 Electrical Characteristics 22.6 A/D Conversion Characteristics Table 22.9 lists the A/D conversion characteristics. Table 22.9 A/D Conversion Characteristics Condition A: VCC = PLL VCC = Dr VCC = 2.4 V to 3.6 V, Vref = 2.4 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.768 kHz, 6 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLL VCC = Dr VCC = 2.7 V to 3.6 V, Vref = 2.7 V to VCC, VSS = PLLVSS = Dr VSS = 0 V, f = 32.
Section 22 Electrical Characteristics 22.7 Flash Memory Characteristics Table 22.10 lists the flash memory characteristics. Table 22.10 Flash Memory Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, Vref = 2.
Section 22 Electrical Characteristics 3. Block erase time (Shows the total period for which the E1-bit FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time value tp (max.) = Wait time after P1 bit set (z) × maximum programming count (N1 + N2) = (Z0 + Z2) × 6 + Z1 × 994 5. Maximum erasure time value tE (max.) = Wait time after E1 bit set (z) × maximum erasure count (N) 6. Minimum times that guarantee all characteristics after programming.
Appendix Appendix A.
Appendix Software MCU Standby Bus Right Program Port Name Operating Power-on Manual Standby Mode or Release Execution State Pin Name Mode Reset Reset Mode Watch Mode State or Sleep Mode Port A 7 T keep T keep keep I/O port 4 and 5 L keep T [OPE=0] T Address output Address output Hardware selected by AEn T bit [OPE=1] 6 Port selection Port B*2 Address output keep T 1 4 to 6 T* keep T keep keep I/O port 7 T keep T keep keep I/O port 4 and 5 L keep
Appendix Software MCU Hardware Standby Bus Right Program Port Name Operating Power-on Manual Standby Mode or Release Execution State Pin Name Mode Reset Reset Mode Watch Mode State or Sleep Mode PF7/φ 4 to 6 Clock output [DDR=0] T [DDR=0] [DDR=0] [DDR=0] Input port Input port Input port input port [DDR=1] [DDR=1] [DDR=1] [DDR=1] Clock output 7 2 PF6/AS* 4 to 6 T H keep H T T H Clock output Clock output [DDR=0] [DDR=0] [DDR=0] Input port Input port Input
Appendix Software MCU Hardware Standby Bus Right Program Port Name Operating Power-on Manual Standby Mode or Release Execution State Pin Name Mode Reset Reset Mode Watch Mode State or Sleep Mode PF0/BREQ 4 to 6 T keep T [BRLE=0] T I/O port [BRLE=1] [BRLE=1] BREQ T 2 PG4/CS0* 7 T keep T 4 and 5 H keep T 6 [BRLE=0] keep keep keep [DDR•OPE=0] T I/O port [DDR=0] T I/O port [DDR•OPE=1] [DDR=1] H CS0 (When sleep T mode)H 2 PG3/CS1* 7 T keep T 4 to 6
Appendix B. Product Model Lineup Product Class H8S/2218 Group Flash memory Version Part No.
Appendix Product Class H8S/2212 Group Flash memory Version Part No.
Appendix C. Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code MASS[Typ.] TFP-100G/TFP-100GV 0.4g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix JEITA Package Code P-LFBGA112-10x10-0.80 RENESAS Code PLBG0112GA-A Previous Code BP-112/BP-112V MASS[Typ.] 0.3g D w S B E w S A ×4 v y1 S y A1 A S S ZD e A L K e J Reference Symbol H B G Dimension in Millimeters Min Nom Max D 10.00 F E 10.00 E v 0.15 D w 0.20 A ZE C B A1 1.40 0.35 e A b 1 2 3 4 5 φ b 6 7 φ 8 9 ×M S A B 10 11 0.45 0.80 0.45 0.50 0.55 x 0.08 y 0.10 y1 0.2 SD SE ZD 1.00 ZE 1.00 Figure C.
Appendix JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KC-A Previous Code FP-64E/FP-64EV MASS[Typ.] 0.4g HD *1 D 48 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 33 49 32 bp c c1 HE *2 E b1 Reference Dimension in Millimeters Symbol Terminal cross section Min 17 ZE 64 1 16 F c A2 Index mark A ZD θ A1 L L1 e *3 Detail F bp x M y D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 10 10 1.45 11.
Appendix JEITA Package Code P-VQFN64-8x8-0.40 RENESAS Code PVQN0064LB-A Previous Code TNP-64B/TNP-64BV MASS[Typ.] 0.12g HD D 33 e 48 32 E HE 49 Lp Reference Symbol 17 ZE 64 1 16 t b b1 x M A1 A c c1 y1 ZD A2 x4 y Figure C.4 TNP-64B and TNP-64BV Package Dimensions Rev.7.00 Dec. 24, 2008 Page 694 of 698 REJ09B0074-0700 D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 Dimension in Millimeters Min Nom 8.0 8.0 0.89 0.005 0.13 0.02 0.18 0.16 0.4 0.60 0.50 0.17 8.2 8.2 1.0 1.
Index Index 16-Bit Timer Pulse Unit......................... 273 A/D Conversion Time............................ 544 A/D Converter ....................................... 535 A/D Converter Activation...................... 323 Absolute Address..................................... 59 Address Space.......................................... 38 Addressing Mode..................................... 58 ADI ........................................................ 546 Advanced Mode...................................
Index Memory Map............................................ 77 NMI Interrupt........................................... 99 Normal Mode ........................................... 34 On-Board Programming......................... 567 Operating Mode Selection........................ 71 Operation Field......................................... 57 Overflow ................................................ 345 Overrun error.......................................... 410 Parity error ...............................
Index PGDR.......................... 269, 636, 644, 652 PORT1 ........................ 217, 639, 648, 655 PORT3 ........................ 224, 639, 648, 655 PORT4 ........................ 227, 639, 648, 655 PORT7 ........................ 230, 639, 648, 655 PORT9 ........................ 232, 639, 648, 655 PORTA ....................... 234, 639, 648, 655 PORTB ....................... 240, 639, 648, 655 PORTC ....................... 246, 639, 648, 655 PORTD ....................... 251, 639, 648, 655 PORTE....
Index Serial Communication Interface............. 363 Shift Instructions ...................................... 51 Single Mode ........................................... 542 Software Protection................................ 583 Stack pointer (SP) .................................... 40 Stack Status .............................................. 89 Stall Operations...................................... 517 Suspend and Resume.............................. 502 Synchronous Operation ........................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2218 Group, H8S/2212 Group Publication Date: 1st Edition, February 2003 Rev.7.00, December 24, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2218 Group, H8S/2212 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0074-0700