Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 109 of 698
REJ09B0074-0700
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8-Bit Bus 16-Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch S
I
1 4 6 + 2m 2 3 + m
Branch address read S
J
Stack manipulation S
K
Legend:
m: Number of wait states in an external device access.
5.6.5 DMAC Activation by Interrupt
The DMAC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used with to activate the DMAC, see section 7, DMA
Controller (DMAC).
Figure 5.7 shows a block diagram of the interrupt controller of DMAC.