Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 138 of 698
REJ09B0074-0700
8-Bit 3-State Access Space (Area 6 and RTC): Figure 6.12 shows the bus timing for area 6 and
RTC area (address = H'FFFF40 to H'FFFF5F). When the areas are accessed, the data bus cannot be
used.
Wait states cannot be inserted.
T
1
T
2
AS*
RD*
D15 to D8*
D7 to D0*
HWR*
LWR*
(16-bit bus
mode)
LWR
*
(8-bit bus
mode)
D15 to D8*
D7 to D0*
Write
Invalid
Invalid
High
High impedance
High impedance
High impedance
Read
T
3
Bus cycle
Address bus
*
φ
Note: * Supported only by the H8S/2218 Group.
Figure 6.12 Bus Timing for Area 6 and RTC