Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 142 of 698
REJ09B0074-0700
16-Bit 3-State Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit 3-state access
space in the H8S/2218 Group. When a 16-bit access space is accessed , the upper half (D15 to D8)
of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
Note: n = 0 to 5
T
3
High impedance
Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)