Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 148 of 698
REJ09B0074-0700
T
1
A
ddress bus
φ
CS0
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
T
1
CS0
AS
T
2
T
1
T
1
RD
A
ddress bus
φ
Data bus
Full access Burst access
Only lower address changed
Read data Read data Read data
Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)