Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 158 of 698
REJ09B0074-0700
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus
Addres buffer
Processor
Internal interrupts
TGI0A
TGI1A
TGI2A
TXI0
RXI0
ADI
USB request signals
DREQ0
DREQ1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Control logic
DMACR1B
DMACR1A
DMACR0B
DMACR0A
DMATCR
DMABCR
Data buffer
Internal address bus
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Legend:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
DMA terminal control register*
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Executive transfer counter register
Note: * Reserved register
Channel 0
Module data bus
Channel 0AChannel 0BChannel 1AChannel 1B
Channel 1
Figure 7.1 Block Diagram of DMAC