Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 171 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
7
6
5
4
DTE1B
DTE1A
DTE0B
DTE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Enable
When DTE = 0, data transfer is disabled and the activation
source selected by the data transfer factor setting is ignored.
If the activation source is an internal interrupt, an interrupt
request is issued to the CPU. If the DTIE bit is set to 1when
DTE = 0, the DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt request to the
CPU.
The conditions for the DTE bit being cleared to 0 are as
follows:
• When initialization is performed
• When the specified number of transfers have been
completed in a transfer mode other than repeat mode
• When 0 is written to the DTE bit to forcibly abort the
transfer, or for a similar reason
When DTE = 1, data transfer is enabled and the DMAC waits
for a request by the activation source selected by the data
transfer factor setting. When a request is issued by the
activation source, DMA transfer is executed. The condition for
the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read
as 0
0: Data transfer disabled
1: Data transfer enabled
3
2
1
0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer End Interrupt Enable
These bits enable or disable an interrupt to the CPU when
transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and
issues a transfer end interrupt request to the CPU.
A transfer end interrupt can be canceled either by clearing
the DTIE bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the
transfer counter and address register again, and then setting
the DTE bit to 1.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled