Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 175 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
Data Transfer Enable
When DTE = 0, data transfer is disabled and the activation
source selected by the data transfer factor setting is ignored.
If the activation source is an internal interrupt, an interrupt
request is issued to the CPU. If the DTIE bit is set to 1 when
DTE = 0, the DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt request to the
CPU.
The conditions for the DTE bit being cleared to 0 are as
follows:
• When initialization is performed
• When the specified number of transfers have been
completed
• When 0 is written to the DTE bit to forcibly abort the
transfer, or for a similar reason
When DTE = 1 and DTME = 1, data transfer is enabled and
the DMAC waits for a request by the activation source
selected by the data transfer factor setting. When a request is
issued by the activation source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read
as 0
6 DTE1 0 R/W Data Transfer Enable 1
Enables or disables data transfer on channel 1.
0: Data transfer disabled
1: Data transfer enabled
5 DTME0 0 R/W Data Transfer Master Enable 0
Enables or disables data transfer on channel 0.
0: Data transfer disabled. In burst mode, cleared to 0 by an
NMI interrupt
1: Data transfer enabled
4 DTE0 0 R/W Data Transfer Enable 0
Enables or disables data transfer on channel 0.
0: Data transfer disabled
1: Data transfer enabled