Datasheet

Rev.7.00 Dec. 24, 2008 Page xxiii of liv
REJ09B0074-0700
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 96
5.3.4 IRQ Status Register (ISR).................................................................................... 98
5.4 Interrupt Sources............................................................................................................... 99
5.4.1 External Interrupts ............................................................................................... 99
5.4.2 Internal Interrupts................................................................................................. 100
5.5 Interrupt Exception Handling Vector Table...................................................................... 101
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 103
5.6.1 Interrupt Control Mode 0 ..................................................................................... 103
5.6.2 Interrupt Control Mode 2 ..................................................................................... 105
5.6.3 Interrupt Exception Handling Sequence .............................................................. 107
5.6.4 Interrupt Response Times .................................................................................... 108
5.6.5 DMAC Activation by Interrupt............................................................................ 109
5.7 Usage Notes ...................................................................................................................... 112
5.7.1 Contention between Interrupt Generation and Disabling..................................... 112
5.7.2 Instructions that Disable Interrupts ...................................................................... 113
5.7.3 Times when Interrupts Are Disabled ................................................................... 113
5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 113
5.7.5 IRQ Interrupt........................................................................................................ 113
5.7.6 NMI Interrupt Usage Notes.................................................................................. 114
Section 6 Bus Controller.................................................................................................... 115
6.1 Features ............................................................................................................................. 115
6.2 Input/Output Pins .............................................................................................................. 117
6.3 Register Descriptions ........................................................................................................ 118
6.3.1 Bus Width Control Register (ABWCR)............................................................... 118
6.3.2 Access State Control Register (ASTCR) ............................................................. 119
6.3.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 120
6.3.4 Bus Control Register H (BCRH).......................................................................... 124
6.3.5 Bus Control Register L (BCRL) .......................................................................... 125
6.3.6 Pin Function Control Register (PFCR) ................................................................ 126
6.4 Bus Control ....................................................................................................................... 127
6.4.1 Area Divisions ..................................................................................................... 127
6.4.2 Bus Specifications................................................................................................ 128
6.4.3 Bus Interface for Each Area................................................................................. 129
6.4.4 Chip Select Signals .............................................................................................. 130
6.5 Basic Timing..................................................................................................................... 131
6.5.1 On-Chip Memory (ROM, RAM) Access Timing ................................................ 131
6.5.2 On-Chip Peripheral Module Access Timing........................................................ 132
6.5.3 External Address Space Access Timing............................................................... 133
6.6 Basic Bus Interface ........................................................................................................... 134
6.6.1 Data Size and Data Alignment (Supported Only by the H8S/2218 Group)......... 134