Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 201 of 698
REJ09B0074-0700
DREQ Signal Level Activation Timing (Normal Mode): Set the DTA bit for the channel for
which the DREQ signal is selected to 1.
Figure 7.19 shows an example of DREQ level activated normal mode transfer.
DREQ
Bus release
Idle Idle IdleRead
Request clear period
Acceptance resumes Acceptance resumes
Minimum of 2 cycles Minimum of 2 cycles
Request clear periodRequest Request
Transfer
source
Transfer
source
Transfer
destination
Transfer
destination
ReadWrite Write
A
ddress bus
DMA control
Channel
φ
DMA
read
DMA
write
Bus
release
DMA
read
DMA
write
Bus
release
[1] [2] [3] [4] [5] [6] [7]
Acceptance after transfer enabling; the DREQ signal low level is sampled on the rising
edge of f, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle.
Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ signal low level is sampled on the rising edge of φ, and the request
is held.)
[1]
[2] [5]
[3] [6]
[4] [7]
Figure 7.19 Example of DREQ Level Activated Normal Mode Transfer
DREQ signal sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ signal low level is sampled while acceptance by means of the DREQ signal is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. Acceptance resumes after the end of the write cycle, DREQ signal low level
sampling is performed again, and this operation is repeated until the transfer ends.
Note: The DREQ signal of this chip is an internal signal of chip, so it is not output from the pin.