Datasheet

Section 8 I/O Ports
Rev.7.00 Dec. 24, 2008 Page 268 of 698
REJ09B0074-0700
8.12.1 Port G Data Direction Register (PGDDR)
PGDDR specifies input or output for the pins of the port G.
Since PGDDR is a write-only register, the bit manipulation instructions must not be used to write
PGDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7 to
5
⎯ Undefined ⎯ Reserved
These bits are undefined and cannot be modified.
4
3
2
1
PG4DDR*
2
PG3DDR*
2
PG2DDR*
2
PG1DDR
0/1*
1
0
0
0
W
W
W
W
(H8S/2218 Group)
Modes 4 to 6:
Setting a PGDDR bit to 1 makes the PG4 to PG1 pins bus
control signal output pins, while clearing the bit to 0
makes the pins input ports.
Mode 7:
Setting a PGDDR bit to 1 makes the corresponding port G
pin an output port, while clearing the bit to 0 makes the
pin an input port.
(H8S/2212 Group)
Setting a PG1DDR bit to 1 makes the corresponding port
G pin an output port, while clearing the bit to 0 makes the
pin an input port.
0 PG0DDR*
3
0 W (H8S/2212 Group)
When EMLE = 1: Pin PG0 function as the H-UDI (TDI)
pin.
When EMLE = 0: If a PG0DDR bit is set to 1, pin PG0
function as output ports. If a PG0DDR bit is cleared to 0,
pin PG0 function as input ports.
Notes: 1. The initial value becomes 1 in modes 4 and 5 and 0 in modes 6 and 7.
2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.
This bit cannot be modified.
3. Reserved in the H8S/2218 Group. If this bit is read, an undefined value will be read.
This bit cannot be modified.