Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 282 of 698
REJ09B0074-0700
Table 9.7 TPSC2 to TPSC0 (channel 2)
Bit 2 Bit 1 Bit 0
Channel TPSC2 TPSC1 TPSC0 Description
2 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on φ/1024
Note: This setting is ignored when channel 1 is in phase counting mode.
9.3.2 Timer Mode Register (TMDR)
The TMDR registers are used to set the operating mode for each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit Bit Name Initial value R/W Description
7, 6 — All 1 — Reserved
These bits are always read as 1 and cannot be modified.
5 BFB 0 R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register.
TGRD input capture/output compare is not generation. In
channels 1 and 2, which have no TGRD, bit 5 is reserved.
It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation