Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 284 of 698
REJ09B0074-0700
9.3.3 Timer I/O Control Register (TIOR)
The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the
TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST
bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the
counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this
setting is invalid and the register operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2
Bit Bit Name Initial value R/W Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B3 to B0
Specify the function of TGRB.
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRA.
• TIORL_0
Bit Bit Name Initial value R/W Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D3 to D0
Specify the function of TGRD.
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C3 to C0
Specify the function of TGRC.