Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 333 of 698
REJ09B0074-0700
Contention between TGR Write and Compare Match: If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written. Figure 9.47
shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N+1
Prohibited
Figure 9.47 Contention between TGR Write and Compare Match