Datasheet

Rev.7.00 Dec. 24, 2008 Page xxxvii of liv
REJ09B0074-0700
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of HD64F2218, HD64F2218U, HD64F2218CU and
HD642217CU......................................................................................................... 3
Figure 1.2 Internal Block Diagram of HD6432217 ................................................................. 4
Figure 1.3 Internal Block Diagram of HD64F2212, HD64F2212U, HD64F2212CU,
HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU....................... 5
Figure 1.4 Internal Block Diagram of HD6432211, HD6432210 and HD6432210S.............. 6
Figure 1.5 Pin Arrangements of HD64F2218, HD64F2218U, HD64F2218CU and
HD64F2217CU (TFP-100G, TFP-100GV)............................................................ 7
Figure 1.6 Pin Arrangements of HD64F2218, HD64F2218U, HD64F2218CU and
HD64F2217CU (BP-112, BP-112V)...................................................................... 8
Figure 1.7 Pin Arrangements of HD6432217 (TFP-100G, TFP-100GV)................................ 9
Figure 1.8 Pin Arrangements of HD6432217 (BP-112, BP-112V) ......................................... 10
Figure 1.9 Pin Arrangements of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211,
HD64F2211U, HD64F2211CU and HD64F2210CU (FP-64E, FP-64EV)............ 11
Figure 1.10 Pin Arrangements of HD6432211, HD6432210 and HD6432210S
(FP-64E, FP-64EV)................................................................................................ 12
Figure 1.11 Pin Arrangements of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211,
HD64F2211U, HD64F2211CU and HD64F2210CU (TNP-64B, TNP-64BV) ..... 13
Figure 1.12 Pin Arrangements of HD6432211, HD6432210 and HD6432210S
(TNP-64B, TNP-64BV) ......................................................................................... 14
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)................................................................ 35
Figure 2.2 Stack Structure in Normal Mode ............................................................................ 35
Figure 2.3 Exception Vector Table (Advanced Mode)............................................................ 36
Figure 2.4 Stack Structure in Advanced Mode........................................................................ 37
Figure 2.5 Memory Map.......................................................................................................... 38
Figure 2.6 CPU Registers ........................................................................................................ 39
Figure 2.7 Usage of General Registers .................................................................................... 40
Figure 2.8 Stack....................................................................................................................... 41
Figure 2.9 General Register Data Formats (1)......................................................................... 44
Figure 2.9 General Register Data Formats (2)......................................................................... 44
Figure 2.10 Memory Data Formats............................................................................................ 45
Figure 2.11 Instruction Formats (Examples) ............................................................................. 57
Figure 2.12 Branch Address Specification in Memory Indirect Mode...................................... 61
Figure 2.13 State Transitions..................................................................................................... 65
Figure 2.14 Flowchart of Method for Accessing Registers Containing Write-Only Bits.......... 69