Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 377 of 698
REJ09B0074-0700
12.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be
written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bits in SSR
have different functions in normal mode and smart card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial Value R/W Description
7 TDRE 1 R/(W)*
1
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1*
2
• When the DMAC is activated by a TXI interrupt
request and writes data to TDR
6 RDRF 0 R/(W)*
1
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive data is
transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1*
2
• When the DMAC is activated by an RXI interrupt and
transferred data from RDR
RDR and the RDRF flag are not affected and retain their
previous values when the RE bit in SCR is cleared to 0.
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.