Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 475 of 698
REJ09B0074-0700
14.3.5 USB FIFO Clear Register 0 (UFCLR0)
UFCLR0 is a one-shot register used to clear the FIFO for each endpoint EP0 to EP3. Writing 1 to a
bit clears the data in the corresponding FIFO.
For IN FIFO, writing 1 to a bit in UFCLR0 clears the data for which the corresponding PKTE bit
in UTRG0 is not set to 1 after data write, or data that is validated by setting the corresponding
PKTE bit in UTRG0.
For OUT FIFO, writing 1 to a bit in UFCLR0 clears data that has not been fixed during reception
or received data for which the corresponding RDFN bit is not set to 1. Accordingly, care must be
taken not to clear data that is currently being received or transmitted. EP1 and EP2, having a dual-
FIFO configuration, are cleared by entire FIFOs. Note that this trigger does not clear the
corresponding interrupt flag. For details, see section 2.9.4, Accessing Registers Containing Write-
Only Bits.
Bit Bit Name Initial Value R/W Description
7, 6 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
5 EP2CLR 0 W EP2 Clear*
0: Performs no operation.
1: Clears EP2 OUT FIFO.
4 EP1CLR 0 W EP1 Clear
0: Performs no operation.
1: Clears EP1 IN FIFO.
3 EP3CLR 0 W EP3 Clear
0: Performs no operation.
1: Clears EP3 IN FIFO.
2 EP0oCLR 0 W EP0o Clear
0: Performs no operation.
1: Clears EP0o OUT FIFO.
1 EP0iCLR 0 W EP0i Clear
0: Performs no operation.
1: Clears EP0i IN FIFO.