Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 476 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
0 — 0 R Reserved
This bit is always read as 0 and cannot be modified.
Note:* When DMA writes are enabled (EP2T1 set to 1 and EP2T0 set to 0 or 1 in UDMAR), it is not
possible to clear the data in the FIFO by writing 1 to EP2CLR. To clear the data in the FIFO,
disable DMA transfers (clear EP2T1 and EP2T0 in UDMAR to 0) and then write 1 to
EP2CLR.
14.3.6 USB Endpoint Stall Register 0 (UESTL0)
UESTL0 is used to forcibly stall each endpoint EP0 to EP3. When the bit is set to 1, the
corresponding endpoint returns a stall handshake to the host, following from the next transfer.
The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for
which decoding is performed by the function, and thus the EP0STL bit is cleared to 0. When the
SetupTS flag in UIFR0 is set to 1, a write of 1 to the EP0STL bit is ignored. For details, refer to
section 14.5.9, Stall Operations.
Bit Bit Name Initial Value R/W Description
7, 6 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
5 EP2STL 0 R/W EP2 Stall
0: Cancels the EP2 stall state.
1: Sets the EP2 stall state.
4 EP1STL 0 R/W EP1 Stall
0: Cancels the EP1 stall state.
1: Sets the EP1 stall state.
3 EP3STL 0 R/W EP3 Stall
0: Cancels the EP3 stall state.
1: Sets the EP3 stall state.
2, 1 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
0 EP0STL 0 R/W EP0 Stall
0: Cancels the EP0 stall state.
1: Sets the EP0 stall state.