Datasheet

Section 1 Overview
Rev.7.00 Dec. 24, 2008 Page 4 of 698
REJ09B0074-0700
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 VCC VCC VSS VSS DrVCC DrVSS NC*
2
NC*
2
NC*
2
NC*
2
NC*
2
NC*
2
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P36(PUPD+)
P32/SCK0/IRQ
4
P31/RxD0
P30/TxD0
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD
P70/CS4 P71/CS5 P74/MRES
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/IRQ7
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT
PF1/BACK
PF0/BREQ/IRQ2
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLVSS
OSC1
OSC2
P96/AN14 P97/AN15
Vref
H8S/2000 CPU
WDT
DMAC
USB
P40/AN0 P41/AN1 P42/AN2 P43/AN3
SCI2
STBY
RES
NMI
FWE*
1
USPND/TMOW
USD+
USD-
UBPM
VBUS
ROM
RAM
RTC
Peripheral data bus
Peripheral address bus
Internal address bus
Internal data bus
Port D
TPU (3 channels)
Interrupts controller
Port E
Port APort B
Bus controller
Port CPort 3
Port FPort G
Port 9Port 4
Port 1 Port 7
SCI0 (High speed UART)
A/D converter (6 channels)
Main clock
pulse
generator
Sub-clock
pulse
generator
Notes: NC (no connection): These pins should not be connected; they should be left open.
1. The FWE pin is provided only in the flash memory version. It should be fixed low.
2. Neither boundary scan nor H-UDI function is available and the pins function as NC.
Figure 1.2 Internal Block Diagram of HD6432217